DP83867IR: RGMII and MII Latency for 10/100Mbps

Hi, Greet,

Thank you for your support. could you please let me know additional question from customer?

1. Jitter for DP83867 and DP83869 : Application note (snla240) support Latency but it doesn't support Jitter. Please share JItter infomation.

2. Customer would like to use Gbit EtherPHY for 100Base-TX and 1000Base-T depend on application requirement. He will would like to switch MII (for 100base-TX) and RGMII( for 1000Base-T) in same board. I heard DP83867 can realize it with external schematiic and DP83869 also realize it with software.

Could you please let me know how to realize it?

3. Customer consider to reduce Latency for 100Base-T. He found RGMII_AF_BYPASS_EN, FAST_RX_DV and LOW_LATENCY_10_100_EN. Are they useful for reducing Latency? And is there any concern to use these?

Regards,
Nagata.

Hi Nagata-san,

1.  1000M signals can't be decoded on scope, the latency measurements are done for round trip and it's difficult to measure the jitter.

2,   I would suggest to use DP83869HM to have same board configure for MII and RGMII. The MII and RGMII pins are multiplexed on the same pins and not board change is needed. It has register configuration to switch between the two clocks. Please refer to register : OP_MODE_DECODE Register Field Descriptions, 0x1DF, bit[5]. and perform soft  reset.

3. These can be used however, it requires the MAC and PHY clock are synchronized and using the same source to avoid ppm difference.

DP83869/DP83867 latency for RGMII to 1000M and RGMII to 100M are among the lowest compare to competition.

Regards,

Geet

Regards,

Geet

HI, Geet,

Thank you very much for your supports.

For #2,
Could you please let me know how to realize for DP83867 with external circuit? I would like to compare the total cost and layout size between DP83869 and DP83867?

Regards,
Nagata.

Could you please support this question?

Regards,
Nagata.

Geet -san,

Is your reply:
>External components needed on DP83867 and DP83869 are similar and shall not impact the BOM cost.
Is it mean DP83867 can switch MII (for 100base-TX) and RGMII( for 1000Base-T) with software (by setting resister?)
And doesn't require additional schematic?

I heard DP83867 requires additional circuit such as additional clock for 1000Base-T. but if your reply is correct, the information is incorrect.

Could you please support this topic? because it is very important infomation.

Regards,
Nagata.

Hi, Geet -san, Team,

I have additional question for Latency. The application note(snla240a) explains the transmit latency and receive latency. They seems to be typical value. customer would like to know max and min value the latency. Could you please give the max/min data for this? or can user use the information as max value?

Regards,
Nagata.  

DP83869 can switch from 

MII to 100M --> RGMII --> 1000M without any board change.

DP83867 supports MII only in 64 pin package variant.

Regards,

Geet

Hi Nagata-san,

As mention some above measurements requires manual decoding of the signal on the MDI  line and max measurement are not practically possible.

Regards,

Geet

Hi, Geet -san,

1.
In your comments 

> DP83867 supports MII only in 64 pin package variant.

I beliver DP83867 support RGMII for 1000Mbps. I search the relation in clock as below.

DP83867 :
100Base-TX MII, TX_CLK=25MHz, RX_CLK=25MHz
1000Base-T RGMII, GTX_CLK=125MHz, RX_CLK=125MHz

DP83869 :
100Base-TX MII, GTX_CLK/TX_CLK = 25MHz, RX_CLK=25MHz?
1000Base-T RGMII, GTX_CLK/TX_CLK = 125MHz, RX_CLK=125MHz

Is the only difference between DP83869 and DP83867 in hardware? Is there another difference?

2. 

Customer should get max latency to prepare customer firmware and fix his specification. I understand the max latency value could not be insurance value but could you please measure it with manual? It should be useful for reference value?

Regards,
Nagata.