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TMDS171: fixed equalization setup

Part Number: TMDS171

Hi

about the TMDS171, how does it work the fixed equalization?

In the datasheet there is a single register to control the equalization gain(0x0D) fot the data lane(without distinction between data lane 0/1/2), but using the EyeScan Tool it seems that the 0x4E and 0X4F registers are controlling the equalization gain of the data lane 0/1/2/3.

If for some reason we want to control the fixed equalization gain what we should do?

Thanks

Regards

Stefano

  • Stefano

    Page 1 0x4E and 0x4F provide the equalizer status, not the equalizer control.

    For fixed equalizer gain, please use the following script example.

    <aardvark>
        <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0"/>
        <i2c_bitrate khz="100"/>
    
    
    
    ======Select  Page 1======
    <i2c_write addr="0x5E" count="1" radix="16">FF 01</i2c_write>/>
    
    === Enable EQ, and set adaptive on/off...
    <i2c_write addr="0x5E" count="1" radix="16">4c 01</i2c_write>/>    === 01 -> Fixed EQ; 03 -> Adaptive EQ
    
    ============================= LANE 0  ========================================
    === Set EQ FTC and LEVEL here...
    <i2c_write addr="0x5E" count="1" radix="16">4d 09</i2c_write>/>    === upper nibble is FTC; lower nibble is level
    === Enable EQ load into lanes...
    <i2c_write addr="0x5E" count="1" radix="16">33 10</i2c_write>/>    === upper nibble is EQ load per lane
    <i2c_write addr="0x5E" count="1" radix="16">33 00</i2c_write>/>    === upper nibble is EQ load per lane
    === Set REG overrides...
    <i2c_write addr="0x5E" count="1" radix="16">A3 68</i2c_write>/>
    
    ============================= LANE 1  ========================================
    === Set EQ FTC and LEVEL here...
    <i2c_write addr="0x5E" count="1" radix="16">4d 0b</i2c_write>/>    === upper nibble is FTC; lower nibble is level
    === Enable EQ load into lanes...
    <i2c_write addr="0x5E" count="1" radix="16">33 20</i2c_write>/>    === upper nibble is EQ load per lane
    <i2c_write addr="0x5E" count="1" radix="16">33 00</i2c_write>/>    === upper nibble is EQ load per lane
    === Set REG overrides...
    <i2c_write addr="0x5E" count="1" radix="16">A3 68</i2c_write>/>
    
    ============================= LANE 2  ========================================
    === Set EQ FTC and LEVEL here...
    <i2c_write addr="0x5E" count="1" radix="16">4d 0a</i2c_write>/>    === upper nibble is FTC; lower nibble is level
    === Enable EQ load into lanes...
    <i2c_write addr="0x5E" count="1" radix="16">33 40</i2c_write>/>    === upper nibble is EQ load per lane
    <i2c_write addr="0x5E" count="1" radix="16">33 00</i2c_write>/>    === upper nibble is EQ load per lane
    === Set REG overrides...
    <i2c_write addr="0x5E" count="1" radix="16">A3 68</i2c_write>/>
    
    ============================= LANE 3  ========================================
    === Set EQ FTC and LEVEL here...
    <i2c_write addr="0x5E" count="1" radix="16">4d 0b</i2c_write>/>    === upper nibble is FTC; lower nibble is level
    === Enable EQ load into lanes...
    <i2c_write addr="0x5E" count="1" radix="16">33 80</i2c_write>/>    === upper nibble is EQ load per lane
    <i2c_write addr="0x5E" count="1" radix="16">33 00</i2c_write>/>    === upper nibble is EQ load per lane
    === Set REG overrides...
    <i2c_write addr="0x5E" count="1" radix="16">A3 68</i2c_write>/>
    
    
    
    ======Read Back 4 bytes from Page 1 address 0x00======
    <i2c_write addr="0x5E" count="0" radix="16">4C</i2c_write>/>
    <i2c_read addr="0x5E" count="4" radix="16">00</i2c_read>/>
    
    
    
    
    ======Select  Page 0======
    <i2c_write addr="0x5E" count="1" radix="16">FF 00</i2c_write>/>
    
    <i2c_write addr="0x5E" count="0" radix="16">09</i2c_write>/>
    <i2c_read addr="0x5E" count="2" radix="16">00</i2c_read>/>
    
    ======Read BERT for each Lane======
    <i2c_write addr="0x5E" count="0" radix="16">18</i2c_write>/>
    <i2c_read addr="0x5E" count="8" radix="16">00</i2c_read>/>
    
    ======Select  Page 1======
    <i2c_write addr="0x5E" count="1" radix="16">FF 01</i2c_write>/>
    
    ======Read Back AEQ Status======
    <i2c_write addr="0x5E" count="0" radix="16">4C</i2c_write>/>
    <i2c_read addr="0x5E" count="4" radix="16">00</i2c_read>/>
    
    ======Select  Page 0======
    <i2c_write addr="0x5E" count="1" radix="16">FF 00</i2c_write>/>
    
    ======Clear BERT======
    <i2c_write addr="0x5E" count="1" radix="16">15 10</i2c_write>/>
    <i2c_write addr="0x5E" count="1" radix="16">15 00</i2c_write>/>
    
    
    
    
    ======Select  Page 0======
    <i2c_write addr="0x5E" count="1" radix="16">FF 00</i2c_write>/>
    
    
    </aardvark>
    

    Thanks

    David