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DS90LV004: Cold sparing or partial power conditions

Jenni Lang
Prodigy 40 points
Part Number: DS90LV004


We have a setup where there’s a chance this part could be powered off while the FPGA driving it could be powered on. Is there any information on if this will cause the board VCC plane to be powered up in this case? We have the enable lines on jumpers which have no digital control.

  • 0
    TI__Guru*** 148630 points

    it's only one Vcc pin, can you send schematic?

  • 0 in reply to Brian Zhou
    Prodigy 40 points

    I guess it's actually VDD in this case.  I can't send a schematic, but there's not really anything to it.  An FPGA on a different board drives to this part which has hardwired Enable pin to ground.  There are 5 of these in each direction.  They are powered from different power sources so there is potential for this to be off while the FPGA is sending data.

  • 0 in reply to Jenni Lang
    TI__Mastermind 43795 points

    Jenni,

    There is no direct specification for IIN whn VDD = 0 Volts in the datasheet.  In addition the absolute maximum Input specification is VDD + 0.3V.  This specification would be violated if the inputs were driven by a LVDS signal when the device VDD = 0 Volts.

    It is very likely that the board will start to power-up through the DS90LV004 input diodes to VDD.

    Regards,

    Lee