• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 34 subscribers
  • Views 511 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83848-EP: DP83848-EP

Don Jaeger
Prodigy 50 points
Part Number: DP83848-EP

Hi Guys,

Troubleshooting a board having the DP83848-EP PHY on it and which refuses to complete a file transfer. Other sibling boards pass, so something defective (PHY, MAC FPGA, or PWB).

- PHY successfully configured by FPGA and then passes Internal and External Loopback

- Scoping PHY signals reveal no stuckies:

- Wireshark detects SYN Req from client, followed by SYN ACK from FTP Server, but no ACK back from Client, so not sure Client received the SYN ACK from server and so the file transfer times out

- Observed that RX_ER, pin 41, pulsed high at the beginning of the attempted FTP (2us wide pulse).

   - What does it mean, given that the PHY passed EXT loopback?

- What is the definition of False Carrier Sense? When reading Reg#10 (PHYSTS) bit11 is set. Does it mean bad RX signals from the isolation Xformer? But ext loopback passed continuously..

Appreciate any help

Thanks,

D.J

  • 0
    TI__Mastermind 18425 points

    Hi Don,

    When testing EXT loop-back, do you use the same type of data packets? Are they standard Ethernet packets or jumbo packets?

    RX_ER high indicated that there was some invalid symbols received during the data transfer. False Carrier and RX_ER can indicate towards a reference clock issue. Can you confirm that clock input to the PHY meets the datasheet requirement? If you are using a crystal for 25MHz input, then check that external capacitors are selected according to the load capacitance in the crystal datasheet. Here is also an app note for reference on selecting peripherals for crystal circuit:http://www.ti.com/lit/an/snla290/snla290.pdf

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 50 points

    Anirudda,

    • According to the data sheet the PHY generates its own ETH packets for the loopback test

    • We scoped the two 25Mhz clocks and they seem to be ok. We also assume that since the BIST external loopback test passes over an extended period of time then the 25Mhz RCV and XMIT clocks are within spec

    • So just to clarify, the RX_ER only responses to comm errors coming in from the server side (Transformer side) not from the Client side (MAC side), is that correct?

    Thanks

    D.J