NS16C2552: About the difference of the register.

Hey Kengo,

I don't have any NS16C2552 device's on hand at the moment to test to see if I can get the same results as the customer.

One suggestion I have is to maybe add a delay between step 5 and 6 or try rereading step 6 twice.

Is it possible for the customer to try our TL16C2552 device out? It looks like it should be pin to pin with the PC16552D device and has the same register map from what I can see.

Thanks,

-Bobby

Hi Bobby.

We tried your advice.

However it did not work.

I can not replacement to TL16C2552.

Could you think of other ways?

Sincerely.
Kengo.

Hey Kengo,

Is it possible for the customer to modify their code? I'm wondering if instead of looking at the IIR they could look at LSR to determine if they can send data. LSR bit 5 show if the THR is empty of full.

Thanks,

-Bobby

Hi BOBBY,

I ask a more question instead of Kengo.

You said "I'm wondering if instead of looking at the IIR they could look at LSR to determine if they can send data. LSR bit 5 show if the THR is empty of full."

Is it possible to interrupt the next Tx Empty without writing the transmit data (releasing the Tx Empty state) using NS16C2552 by this method?

Regards,

Y.Ottey

Hey Y.Ottey,

"Is it possible to interrupt the next Tx Empty"

I'm not 100% sure what you are asking. Can you phrase the question differently or maybe walk me through what process you are trying to do/check?

Do you mean if you read LSR, you would expect IIR to tell you that THR is empty if you read IIR (after reading LSR to check THR empty?)?

Thanks,

-Bobby

Hi BOBBY

Thank you for your reply.

Sorry for the bad question.

I ask another question

1. Why did our customer use NS16C2552TVS and became Not set in the sixth step below because the register map is different? If you have another reason, please let me know.

/Configuration/

1. FCR : Tx and Rx FIFO Enable(bit0) is '1'

2. IER : Tx_Empty Int Enable(bit1) is '1'

3. IIR : Interrupt Status(bit3) read

-> We checked it was set 0x2(= Transmit data ready)

-> PC16552D : Set , NS16C2552 : Set

4. IER : Tx_Empty Int Enable(bit1) clear

5. IER Tx_Empty Int Enable(bit1) is '1'

6. IIR : Interrupt Status(bit3) read

-> We checked it was set 0x2(= Transmit data ready)

-> PC16552D : Set , NS16C2552 : Not Set

7. THR : Data write

8. Start from No.4 to No.6

-> We checked it was set 0x2(= Transmit data ready)

-> PC16552D : Set , NS16C2552 : Set

2. When our customer confirmed the operation with NS16C2552TVS according to the above procedure, unlike PC16552DV, NS16C2552TVS did not generate the next Tx Empty interrupt unless the transmission data was written once.
Is this normal for NS16C2552TVS operation?

Regards,

Y.Ottey