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DS90UH948-Q1: Back Channel Frequency

Jared Becker
Genius 11845 points
Part Number: DS90UH948-Q1

Hi Team,

I am trying to determine the frequency of the back channel. In the 948 datasheet, there is register 0x23, bit 6, which is BC_FREQ_SELECT. This bit refers to dividing down the OSC CLOCK DIVIDER in register 0x32, but I can't find register 0x32 in the datasheet.

Ultimately, my question is, what is the frequency of the backchannel? It sounds like it can be set to a certain frequency within a range. Can you please let me know what that range is?

Thank you,

Jared

  • 0
    TI__Guru** 103215 points

    Hello Jared,

    The back channel can be set to 5, 10, or 20Mbps based on BC_FREQ_SELECT and BC_HS_CTL. Here are the settings:

    This table is in section 7.3.9.2 "Back Channel Configuration"

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Genius 11845 points

    Hi Casey,

    Thanks for the insight. Do you know if the data is transferred at 1 bit per cycle, so the frequency is 5MHz, 10MHz, or 20MHz respectively?

    Best,

    Jared

  • 0 in reply to Jared Becker
    TI__Guru** 103215 points

    Hello Jared,

    The back channel is manchester encoded so the frequency equals the symbol rate (5MHz = 5Mbps). But the back channel frame is not entirely user data. There are sync bits and encoding bits in the back channel frame so the effective data rates for GPIO as an example are lower than the data rate of course. You can see effective data rates in the datasheet for back channel GPIO. 

    Best Regards,

    Casey