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DS90UB941AS-Q1: Some question

Shu-Cheng LIN
Guru 11785 points
Part Number: DS90UB941AS-Q1


Hi Sirs,

Sorry to bother you.

Currently, there is a problem with the debug DS90UB941AS-Q1, the deserializer ID can be read, but the FPD link cannot be locked, probably in the DSI input section.
LCD resolution is 1024 x 600. single DSI. STP cable.


Is there a sample code of DS90UB941AS-Q1 initial and HW setting recommendations for reference?


In addition, in the DSI Indirect Register, what settings need to be made in addition to TSKIP_CNT?

  • 0
    TI__Guru** 103215 points

    Hello Shu-Cheng,

    Can you please confirm the following details for your system?

    - MODE_SEL strappings

    - DSI source mode: (non-burst pulse, non-burst event, burst)

    - DSI frequency and desired PCLK frequency 

    - Desired FPD III clocking mode: (PCLK from DSI, PCLK from external REFCLK)

    - Which deserializer is being used and how many FPD III lanes?

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    Update as below

    - MODE_SEL strappings

    => Mode_sel0


    => Mode_sel1


    - DSI source mode: (non-burst pulse, non-burst event, burst)

    => non-burst mode with sync pulse

     

    - DSI frequency and desired PCLK frequency 

    => pixel clock=51.2MHz,

         DSI data rate=307.2MHz,

         DSI frequency = 153.6MHz

     

    - Desired FPD III clocking mode: (PCLK from DSI, PCLK from external REFCLK)

    => PCLK from DSI

     

    - Which deserializer is being used and how many FPD III lanes?

    => Deserializer is DS90UB928QSQX/NOPB. Use one FPDIII lane only.

     

     

     

     

     

  • 0 in reply to Shu-Cheng LIN
    TI__Mastermind 30515 points

    Hello

    yes, the Tskip_CNT must be set dependent on the DSI clock freq.

    in your case, pls check if the reg. 0x56 selects the correct clock source or not, also, please set the Tskp_cnt with below register setting.

    WriteI2C (0x40,0x04) //Select DSI Port 0 digital registers if this is your use case
    WriteI2C (0x41,0x05) //Select DPHY_SKIP_TIMING register
    WriteI2C (0x42,0x09) //Write TSKIP_CNT value for 153.6 MHz DSI clock frequency (pls check d/s on this calculation)

    beside, pls measure the DSI input clock signal and dump 941as registers for further analysis if Tskip_cnt can't resolve your issue.

    regards,

    Steven