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Original question:

DS90UB954-Q1: DS90UB954-953 MIPI output Lane

DS90UB954-Q1: DS90UB954-953 maximum line length

Juergen Suetterlin
Prodigy 240 points
Part Number: DS90UB954-Q1

Hello,

in a related post it was said, that in a 953/954 system the 953 can have 4 CSI lanes and while the 954 can have 2 lanes.

Since this means that we write faster in than we read out, I assume that one of both chips must have a line buffer.

If so, can you tell me the size of that line buffer? Is there a maximum line length which can be transmitted?

We intent to transmit non-video data over a FPD-LINK from an FPGA. Could we have an endless Line length, or at least the maximum 2^16 bytes of the CSI specification?

Best regards

  • 0
    TI__Mastermind 30515 points

    HI Suetterlin,

    thank you to touch TI on-line.

    1. Yes, UB953/UB954 can support 2lanes or 4lanes, but the total CSI2 data bandwidth are same, for example, if you set UB953 csi2 as 4lanes and the lane rate is 800Mbps/lane, then the UB954 can be set as 2lanes but the lane rate MUST be set as 1.6Gbps/lane

    2. UB954 has internal video buffer for one line length, which is ~16Kbytes, if the video data type is RGB888, then the line length can be up to 5K.

    ///////////////////UB954 datasheet //////////////////

    7.4.25 Video Buffers
    The DS90UB954-Q1 implements two video line buffer and FIFO, one for each RX channel. The video buffers
    provide storage of data payload and forward requirements for sending multiple video streams on the CSI-2
    transmit ports. The total line buffer memory size is a 16-kB block for each RX port.
    The CSI-2 transmitter waits for an entire packet to be available before pulling data from the video buffers.

    best regards,

    Steven