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Original question:

RTOS/DS90UB933-Q1: 933/934 driver code

DS90UB933-Q1: support application for DS90UB933/DS90UB934

Chen Melina
Intellectual 945 points

Part Number: DS90UB933-Q1

Hi

We got a problem when we debug TI FPD LINK Ser+Deser solution, we may need your help to solve it.

A. Environment Setup:

    1.Image format: YUV422

    2.Pixel Solution: 1080*1920

    3.PCLK output from ISP:100MHz

    4.FPD Serial: DS90UB933

    5.FPD Des:    DS90UB934

    6.Cable: Coax with 12V POC

 

B. Phenomenon Description:

   1.ISP can output HS/VS/PCLk to DS90UB933

   2.high level on PASS and LOCK of DS90UB934, this means there is a valid link on the cable, right?

   3.OEN/OSS_SEL/PDB is set high in registers of DS90UB934.

 

C. Problem Description

   but no signal on PCLK and Data[0:7] on DS90UB934.

 

D. Help we want

    1. Analysis and test suggestion to find the problem Root cause.

    2. proposd register setup example based on our Environment Setup of Part A.

  • 0
    TI__Guru** 117160 points

    Hello Chen,

    having LOCK does not mean there is incoming data into the 933.

    Debugging steps:

    1) double check Mode pins settings on both sides (933 and 934). Make sure the modes are matching.

    2) measure the Oscillator output on the camera side and make sure it is connected properly to the imager and 933 as per d/s.

    3) measure if data is there and correct at Vsync, Hsync and CLK + 1 data lane incoming into the 933.