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DS90UB954-Q1: Register setting sequence

Tomoaki Yoshida91
Genius 5255 points
Part Number: DS90UB954-Q1

Hi team,

I want advice on the order of register settings.

I think that  special order is required when setting the 954 registers.

However, if we actually use it, please let me know if there is a recommended register setting order.

What I'm interested in is how to do it if communication from 953 starts in the middle of setting.

CSI output is off by default, so we will enable 0x33 [0] CSI ENABLE after all settings have been made.

Best regards,

Tomoaki Yoshida

  • 0
    TI__Guru** 107740 points

    Hello Tomoaki,

    please refer to figure 57 in the 954 d/s page number 151.

  • 0 in reply to Hamzeh Jaradat
    Genius 5255 points

    Hi Hamzeh-san,

    Thank you for your support.

    I understand.

    I will set 0x33 [0] CSI ENABLE to enable after all setting have been done.

    Is the data set in the output FIFO when  0x33 [0]  will be enabled?

    Is it reset once at the same time as Enable, or is the data from the time the RX port is enabled remaining in the FIFO?

    I want to check if unnecessary data is output when SERDES is reset for some reason while it is running.

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    TI__Guru** 107740 points

    Hello Tomoaki-san,

    The 954 deserializer has two FIFO, one for each RX input port. Each FIFO can support maximum 2 lines of data.

    Please make sure that Forwarding should be disabled in Reg 0x20 (FWD_CTL1 register) prior to enabling or disabling the CSI output in Reg 0x33 (CSI_CTL).


    The forwarding control pulls data from the Video buffers for each FPD3 Receive port and forwards the data to the CSI-2 output interface.  It also handles generation of transitions between LP and HS modes as well as sending of Synchronization frames.

  • 0 in reply to Hamzeh Jaradat
    Genius 5255 points

    Hi Hamzeh-san,

    Thank you for your support.

    I understand that if there is some data in the RX port FIFO before the CSI output is enabled, it will be expelled to the CSI output.

    We will enable the RX port after enabling the CSI output.

    Best regards,

    Tomoaki Yoshida