DS125DF1610: BERT

Ilya Mazurenko

Part Number: DS125DF1610
Other Parts Discussed in Thread: DS280BR820EVM, LMX2581, DS280BR820, SIGCONARCHITECT, , DS280DF810EVM, DS280DF810, DS250DF810

Hello Team,

My customer are going to use DS125DF1610 in their new project and asked several questions.
Currently they have DS280BR820EVM board and are going to test logic and ability to run BERT.

As described in 12-Gbps BERT Board Reference Design(DS125DF1610) - to launch BERT it needs to connect LMX2581 to input of one of the channels.

1) What frequency should be on that input of DS280BR820 and what setting should they use to run at 10.3125 Gbps?

2) Do they understand correctly, that it need to use a separate group of channels for generation and a separate group of channels to test PRBS?

3) It is clear that the Error Count (bit) is read from the chip by the registers Reg_0x83 [2: 0] = prbs_err_cnt [10: 8], Reg_0x84 [7: 0] = prbs_err_cnt [7: 0].
How does Error Rate (bits/min) and Bit Count calculated in SigConArchitect?

Thank you in advance!

BR,
Ilya

over 6 years ago

0 Rodrigo Natal over 6 years ago

TI__Mastermind 19235 points

Hi,

The DS280BR820 is a completely different product than the DS125DF1610. The DS280BR820 is a redriver and not a retimer, and it lacks PRBS functions. Please have the customer purchase a DS125DF1610EVM via the order link below.

http://www.ti.com/tool/DS125DF1610EVM

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 Ilya Mazurenko over 5 years ago in reply to Rodrigo Natal

Expert 1300 points

Hello Rodrigo,

I missprinted, actually they have DS280DF810EVM (Retimer). I am sorry.

Could you help please with our customer's questions:

As described in 12-Gbps BERT Board Reference Design(DS125DF1610) - to launch BERT it needs to connect LMX2581 to input of one of the channels.

1) What frequency should be on that input of DS280DF810 and what setting should they use to run at 10.3125 Gbps?

2) Do they understand correctly, that it need to use a separate group of channels for generation and a separate group of channels to test PRBS?

3) It is clear that the Error Count (bit) is read from the chip by the registers Reg_0x83 [2: 0] = prbs_err_cnt [10: 8], Reg_0x84 [7: 0] = prbs_err_cnt [7: 0].
How does Error Rate (bits/min) and Bit Count calculated in SigConArchitect?

BR,
Ilya

0 Rodrigo Natal over 5 years ago in reply to Ilya Mazurenko

TI__Mastermind 19235 points

Hi Ilya. My inputs below.

1) What frequency should be on that input of DS280DF810 and what setting should they use to run at 10.3125 Gbps?

You may use a 1010 square wave/sinusoid at a frequency of divider as low as 8 relative to the 10.3125Gbps data rate.
A sinusoid with frequency that is divide by 8 of 10.3125Gbps would be at 644.53125 MHz

2) Do they understand correctly, that it need to use a separate group of channels for generation and a separate group of channels to test PRBS?

Correct. We do not recommend simultaneously generating and checking PRBS on the same channel

For ease of reference the routines for enabling PRBS generator and checker on the DS250DF810 are included below.

Table. Register Writes to Enable PRBS Generator

STEP	SHARED/ CHANNEL REGISTER SET	OPERATION	REGISTER ADDRESS [HEX]	REGISTER VALUE [HEX]	WRITE MASK [HEX]	COMMENT
1	Channel	Write	2E	04	04	Set prbs_pattern_sel[2] for selecting PRBS options: 0: Allows selection of PRBS7, PRBS9, PRBS11 or PRBS 15 1: Allows selection of PRBS23, PRBS31, PRBS58, or PRBS63
2	Channel	Write	30	01	03	Select pattern by setting prbs_pattern_sel[1:0]: 2’b00: PRBS7 (or PRBS23) 2’b01: PRBS9 (or PRBS31) 2’b10: PRBS11 (or PRBS58) 2’b11: PRBS15 (or PRBS63)
3	Channel	Write	1E	10	10	Turn on serializer (ser_en=1)
4	Channel	Write	79	00	20	Set prbs_gen_en=0
5	Channel	Write	79	20	20	Set prbs_gen_en=1
6	Channel	Write	30	00	08	Set prbs_en_dig_clk=0
7	Channel	Write	30	08	08	Set prbs_en_dig_clk=1
8	Channel	Write	A5	80	E0	Select PRBS Generator for post-lock output mux

Table. Register Writes to Enable PRBS Checker

STEP	SHARED/ CHANNEL REGISTER SET	OPERATION	REGISTER ADDRESS [HEX]	REGISTER VALUE [HEX]	WRITE MASK [HEX]	COMMENT
1	Channel	Write	0D	00	80	Turn on the de-serializer
2	Channel	Write	79	40	40	Set prbs_chkr_en=1
3	Channel	Write	30	00	08	Set prbs_en_dig_clk=0 to disable the digital clock
4	Channel	Write	30	08	08	Set prbs_en_dig_clk=1 to enable the digital clock
5	Channel	Write	30	10	10	Force reload of PRBS checker seed
6	Channel	Write	30	00	10	Undo force reload of PRBS checker seed
7	Channel	Write	82	40	40	Reset PRBS counters
8	Channel	Write	82	00	40	Un-reset PRBS counters
9	Channel	Read	01			Read PRBS status: Reg_0x01[6]: PRBS pattern polarity detection 1’b0: Polarity detected is not inverted 1’b1: Polarity detected is inverted Reg_0x01[4]: PRBS sequence detected 1’b1: Pattern detected 1’b0: No pattern detected Reg_0x01[3:1]: PRBS detect result 3’b000: PRBS7 3’b001: PRBS9 3’b010: PRBS11 3’b011: PRBS15 3’b100: PRBS23 3’b101: PRBS31 3’b110: PRBS58 3’b111: PRBS63

Table 48. Register Writes to Read PRBS Checker Error Count

STEP	SHARED/ CHANNEL REGISTER SET	OPERATION	REGISTER ADDRESS [HEX]	REGISTER VALUE [HEX]	WRITE MASK [HEX]	COMMENT
1	Channel	Write	82	80	80	Freeze the current error counter
2	Channel	Read	83			Reg_0x83[2:0] = prbs_err_cnt[10:8]
3	Channel	Read	84			Reg_0x84[7:0] = prbs_err_cnt[7:0]
4	Total error count = ((Reg_0x83 & 0x03) << 8) \| Reg_0x84
5	Channel	Write	82	00	80	Un-freeze the PRBS error counter

Table. Register Writes to Clear PRBS Checker Error Count

STEP	SHARED/ CHANNEL REGISTER SET	OPERATION	REGISTER ADDRESS [HEX]	REGISTER VALUE [HEX]	WRITE MASK [HEX]	COMMENT
1	Channel	Write	82	40	40	Reset PRBS counter
2	Channel	Write	82	00	40	Un-reset PRBS counter

3) It is clear that the Error Count (bit) is read from the chip by the registers Reg_0x83 [2: 0] = prbs_err_cnt [10: 8], Reg_0x84 [7: 0] = prbs_err_cnt [7: 0].
How does Error Rate (bits/min) and Bit Count calculated in SigConArchitect?

Bit error rate = (number of bit errors)/ (number of bits transmitted)\
The number of bits transmitted is calculated by using the time elapsed multiplied by the data rate

0 Ilya Mazurenko over 5 years ago in reply to Rodrigo Natal

Expert 1300 points

Hello Rodrigo,

Thank you for the detailed answer!

The customer asked to clarify:
1) Can they use frequency divided by 32? (not 8)
161,1327125 MHz for 10,3125 Gbit/s;
402,83123125 MHz for 25,78125 Gbit/s;

3) About BER(bit error rate):
The counter of bit errors at a speed of 10.3125 Gbit/s is overfilled in for 1.986 * 10 ^ -7 if we count all the bits as incorrect ones.
How can they prevent the counter from overflowing so as not to miss the incorrectly received bits? And correctly calculate the BER.

BR,
Ilya

0 Rodrigo Natal over 5 years ago in reply to Ilya Mazurenko

TI__Mastermind 19235 points

Divde by 32 is ok when data rate is 25Gbps but not for 10.3125Gbps. Divide by 16 may be used for 10Gbps.

If the customer has configured the CDR rate correctly and Rx EQ is optimal the customer should not be seeing any bit errors. Can you provide a full channel registers dump for this case?

Thanks,

Rodrigo Natal

HSSC Applications Engineer

Interface

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DS125DF1610: BERT