DS91M040: M-LVDS compatibility with FPGA LVDS

Haje

Part Number: DS91M040

Hello

I've been searching for statements about compatibility of LVDS and M-LVDS but haven't reached a conclusion.

We plan to use M-LVDS with DS91M040 to interface two or more processor systems.

In some cases, it will be necessary to interface with an existing FPGA card (Spartan 3E) that uses directly the LVDS I/O of the Spartan3E. I cannot change this card.

If I understand correctly, the combination of FPGA LVDS driver and M-LVDS Receiver should not be a problem.

In case of M-LVDS Transmitter to FPGA Receiver, I'm not so sure.

For example, the maximum differential output voltage of the DS91M040 Driver is given as 650mV. The maximum differential input voltage of the Spartan3E is 600mV.

Is it generally correct to say:

1) LVDS driver is usually compatible with M-LVDS receiver

2) M-LVDS driver is usually incompatible with LVDS receiver

How could I make the M-LVDS driver compatible with the LVDS receiver?

I could lower the 100Ohm termination resistor on the transmitter side to 82Ohm, this should result in a maximum differential output voltage of less than 600mV.

Would this work? If yes, is it a good idea? What are the pitfalls?

Best regards

Haje

over 5 years ago

0 David (ASIC) Liu over 5 years ago

TI__Guru**** 157496 points

Haje

1) The LVDS transmitter can support multi-drop (driving multiple receivers). Notice that you can have only one termination resistor which should be placed on the last receiver.

2) M-LVDS transmitter can work with a regular LVDS receiver.

Thanks

David

0 Haje over 5 years ago in reply to David (ASIC) Liu

Prodigy 150 points

Hello David

Thank you for your reply.

<< 2) M-LVDS transmitter can work with a regular LVDS receiver.

Does this mean that you don't think it will be a problem in the case I described where the maximum differential output voltage (650mV) of the M-LVDS transmitter would overdrive the LVDS receiver which has a maximum differential input voltage of only 600mV?

Regards

Haje

0 David (ASIC) Liu over 5 years ago in reply to Haje

TI__Guru**** 157496 points

Haje

The LVDS input voltage range is from 0 to 2.4V as shown below. If FGPA max differential input voltage is only 600mV, it does not look like it is a fully LVDS recevier, Can you please clarify on the FPGA RX?

Thanks

David

0 Haje over 5 years ago in reply to David (ASIC) Liu

Prodigy 150 points

Hello David

Ah, thank you, that makes sense.

From page 122 of www.xilinx.com/.../ds312.pdf

Regards

Haje

0 Haje over 5 years ago in reply to Haje

Prodigy 150 points

0 Haje over 5 years ago in reply to Haje

Prodigy 150 points

Sorry, but pasting a screenshot does not seem to work. It works in the editor but it does not appear in the message.

Now trying with insert file

From page 122 of

0 Lee Sledjeski over 5 years ago in reply to Haje

TI__Mastermind 43795 points

It's not exactly to the LVDS specification, but there will not be any issues with direct MLVDS interface. I believe the FPGA is limited to a 600mV VID because they do not want the input signal to go below GND or above VCC on the FPGA. Either condition could forward bias ESD circuits.

Regards,

Lee

0 Haje over 5 years ago in reply to Lee Sledjeski

Prodigy 150 points

Hello Lee

Thank you!

Best regards

Haje

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DS91M040: M-LVDS compatibility with FPGA LVDS