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TL16C2550: td5 timing

cafain
Mastermind 6775 points

Part Number: TL16C2550

HI, staff

I have a question about the falling timing of _CSA and _CSB of TL16C2550.

Used at 3.3V.
What is the meaning of the time specified in data sheet page13 td5 and td8?

1. After addressing, the transition time of _CSA and _CSB fall time should be at least 7ns.

2. After addressing, the fall time of _CSA and _CSB is changed within 7ns at the minimum.

Which of the above “1” or “2” is correct?
Can td5 and td8 be "0nsec" (simultaneous transition)?

best regards
cafain

  • 0
    TI__Guru 53535 points

    Hi Cafain,

    td5 and td8 refer to the time delay between when addressing occurs to when _CSA / _CSB should see a new input. This means the address must be held for at least this amount of time before _CSA /_CSB can be changed. The address(A2-A0) and _CSA / _CSB pins should not be changed at the same time when working on the same process. 

    I hope this helps to clarify. Let me know if you have any more questions.

    Regards,

    Eric

  • 0 in reply to Eric Schott1
    Mastermind 6775 points

    HI, Eric-san

    I understand that it is the setup time of Address signal with respect to CSx signal.
    Thank you very much.
    cafain