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DS90UB933-Q1: DS90UB933 with DS90UB934 some of data lost durning transmission

Steven He92
Expert 2125 points
Part Number: DS90UB933-Q1

Dear Sir,

my customer use DS90UB933 to do design with DS90UB934.

He have a issue: some time will happen data loss at DS90UB934 side when DS90UB933 with DS90UB934 data transmission.

I provide Coaxial cable spec. & POC circuit to you reference.

Please you kindly review & advise.

Thanks!

Steven

D1370115BT(1 37).pdf

  • 0
    Prodigy 60 points

    933 Hsync & Vsync the signal is normal

    but 934 Hsync & Vsync the signal will interrupt randomly

    waveform as below.

  • 0 in reply to David Chien46
    TI__Mastermind 30515 points

    Hi,

    I think the link has detected error in UB34 side so you can observe the plot above. The PoC sch. sounds well but pls be careful of the layout, in TI's d/s, it has POC layout recommendation also you can refer to UB934EVM board.

    From the picture, it sounds the cable is NOT known by us, what type is it?

    best regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    TI__Mastermind 30515 points

    Also, the PCLK jitter, does it meet the request in UB933 d/s? how about the POC voltage in your case?

    best regars,d

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Expert 2125 points

    Dear Sir,

    PLC jitter, please you refer below waveform around 14nS~15nS is OK? & The POC was setting 5V

    customer was use ON-Semi_ AR0144, refer attached file is DS933/ 934 register setting have any need to modify?

    Can use external OSC use 54MHz ? (I saw DS90UB933 ds table1 only list 48MHz).

    Thanks!

    Steven

    Fullscreen TI933TI934 settings_for AR0144 Ver.20190912.txt Download 
    Slave Address :  933(W:0xB0�@R:0xB1)    934(W:0x60  R:0x61)
Address : 1 bytes
Data : 1 bytes 

DrvDS90UB934_Updata( 0x4C , 0x12 ); //Reg : 0x4C , Data : 0x12
DrvDS90UB934_Updata( 0x0D , 0x09 );
DrvDS90UB934_Updata( 0x58 , 0x58 );
DrvDS90UB934_Updata( 0x3B , 0x00 );
DrvDS90UB934_Updata( 0xB0 , 0x08 );
Delay 5 ms
DrvDS90UB934_Updata( 0x5C , 0xB0 );	
DrvDS90UB934_Updata( 0x08 , 0x17 );
DrvDS90UB934_Updata( 0x0F , 0x03 );
DrvDS90UB934_Updata( 0x5D , 0x20 );	
DrvDS90UB934_Updata( 0x65 , 0x20 );
DrvDS90UB934_Updata( 0x6D , 0x7E );

DrvDS90UB933_Updata( 0x0E , 0x15 );
Delay 250 ms
DrvDS90UB933_Updata( 0x0E , 0x99 );
DrvDS90UB933_Updata( 0x01 , 0x20 );
DrvDS90UB933_Updata( 0x03 , 0x45 );
DrvDS90UB933_Updata( 0x05 , 0x06 );
DrvDS90UB933_Updata( 0x35 , 0x01 );
DrvDS90UB933_Updata( 0x0C , 0x15 );
DrvDS90UB933_Updata( 0x0D , 0x99 );

  • 0 in reply to Steven He92
    Prodigy 60 points

    Dear Sir

    further explain

    I will try external OSC. mode , can help check if use 54MHz OSC input GPIO3 and GPIO2 output 27MHz for sensor MCLK than PCLK will output 74.25MHz for TI 933, in the external OSC. mode PCLK 74.25MHz is OK?

    Thanks!

  • 0 in reply to David Chien46
    TI__Mastermind 30515 points

    no, it can't work. pls check the d/s on detailed clock setting request. for raw10 mode, the PCLK freq. must be 2x of external clock freq.

    bet regards,

    Steven