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DS90UR124: about when lost LVDS input for deserializer

ACGUY
Guru 11170 points

Part Number: DS90UR124

Hello E2E,

I know that this device transition to be power down mode when lost the LVDS input. Why doesn't TI list it in the datasheet?

Regards,

ACGUY

  • 0
    TI__Guru** 103215 points

    Hello ACGUY,

    Can you explain a little bit more clearly about exactly the behavior you are seeing which you would like us to include in the datasheet? Do you have any scope shot to show the phenomenon?

    Thanks,

    Casey 

  • 0 in reply to Casey McCrea
    Guru 11170 points

    Hello Casey,

    Thank you for see my posted. Please see the following URL.

    Waveform 1, Left-High is 3.0V (pulled-up to 3.0V bias by 10-kohm), Right-High is 3.3V (states Locked). When LOCK-pin voltage is bias voltage, it is indicated LOCK-pin is High-Z. It is inconsistent to table-2. I think that this LOCK-pin High-Z is indicated power down for receiver.

    Is my idea correct?

    Regards,

    ACGUY

  • 0 in reply to ACGUY
    TI__Genius 12866 points

    Hi ACGUY,

    I am looking into the question raised in the other thread. Will get back to you once we reach an conclusion.

    Best Regards,

    Charley Cai

  • 0 in reply to Charley Cai
    TI__Guru** 103215 points

    Hello ACGUY,

    Sorry for the delay. Since this is an older legacy device it is taking us some additional time to local test hardware and design documentation. We are still working on the issue. 

    Best Regards,

    Casey 

  • 0 in reply to ACGUY
    TI__Genius 12866 points

    We did a curve tracing on the lock pin.

    When clock signal is removed from TCLK pin on the serializer, the LOCK pin on UR124 will be tristate.

    When clock signal is supplied to TCLK pin and you try to create a unlock condition of disconnecting RIN+ cable, the LOCK pin on UR124 will be LOW.

    Best Regards,

    Charley Cai