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TMDS261B: About tmds261B

user6123336
Prodigy 30 points
Part Number: TMDS261B 
I confirmed the circuit diagram of TMDS361EVM. I took this circuit configuration using TMDS261B and connected all the DVI cables. When I turn on the device, the device displays the CH1 side.
When I switched the display to Ch2, I confirmed that there was no signal because HPD was “High” from startup and EDID was not read.
In order to cope with this, I think that it is necessary to take the configuration of Figure 46 of the data sheet.


Question 1: Is there a way to solve it without taking the circuit configuration shown in Fig. 46 in the data sheet?
Question 2: When the circuit configuration shown in Figure 46 of the data sheet is used, the MPU and EEPROM must be connected. 
　　　　　I thought about how the MPU should behave as follows, but please make sure it is correct. I am thinking of realizing it with FPGA. 
　　　　　(1) Set HPD_SINK to LOW. 
　　　　　(2) The MPU (FPGA) reads EDID from the sink and writes it to the EEPROM. 
　　　　　(3) Set S1 and S2 to switch channels and read the EDID on the source side.

Question 3: I think that switching between S1 and S2 in Question 2 is possible because HPD_SINK is Low.
Is that idea correct?
  • 0
    TI__Guru**** 176281 points

    Please refer to Table 1 of the TMDS261B datasheet for the S1 and S2 control pins setting. 

    Per the HDMI spec, the source assumes that any voltage within the range specified for high voltage level by the spec indicates that a sink is connected and that E-EDID is readable. 

    When switch from CH1 to CH2, HPD_SNK needs to toggle from high -> low -> high to indicate the change in the source.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 30 points

    ・As a result of confirming when all the HDMI connectors are connected, the following phenomenon occurred.

    S1=S2=H　HPD1=HPD2=HPD_SINK

    Is this correct？（In Figure 45, HPD1 and HPD2 (HPD[1:2]) are written to have the same logic.)


    ・I would like to receive an answer regarding Q2, which I asked last time.

    ・When the MPU in Figure 46 is changed to FPGA, Please let me know if you know how to control EDID memory with FPGA.

  • 0 in reply to user6123336
    TI__Guru**** 176281 points

    Please refer to Table 1, when S1=S2=H, only port 1 is selected, termination of port 2 are disconnected.

    E-EDID is read using the DDC bus and DDC utilizes the I2C bus. If using FPGA to read the E-EDID, please make sure the FPGA acts as a I2C master. Please follows the DDC I2C function description section and DDC I2C behavior section in the Application Information portion of the datasheet. For more detail on I2C, please refer to the I2C spec.

    Thanks

    David