DP83848Q-Q1: DP83848Q-Q1: DAP required to be grounded?

yes, I understand that the DAP should be connected to the ground plane for heat dissipation purposes.

I have already fixed the board design for the next iteration to the ground plane for heat dissipation purposes.

This doesn't answer my question.

The DP83848Q-Q1 on the current iteration of the board does not respond to MDIO commands.

If the DAP is not electrically connected to ground, will this cause the DP83848Q-Q1 to not respond to MDIO commands?

Hello Morita,

Thanks for clarifying. I would not expect any issues with the MDIO commands, because the PHY has other dedicated pins for analog and digital ground.

Please try connecting the DAP and let us know if you see the issue resolved.

Thanks,

Vibhu

Grounding the DAP did not help.

Toshi

Hello Toshi,

It seems to be that the issue is not with the DAP being grounded then. Please double check your schematic with the datasheet, you may also refer to https://www.ti.com/lit/an/snla079d/snla079d.pdf.

Thanks,

Vibhu

The MDI interface clock on my board is 1.25 Mhz, so it should not be sensitive to board layout issues.

Toshi

Hello Toshi,

If using MII, can you check to see if there is a clock on pin 2 TX_CLK, it should be either 2.5 MHz or 25 MHz depending on 10M/100M mode.

Thanks,

Vibhu

I see the DP83848 emitting fast link pulses on the Ethernet side.

I am using RMII, so TX_CLK is not used.

Toshi

Hello Toshi,

Can you check to see if there are any link pulses on the signals? Also what is the current consumption of the device? This may help narrow down the status of the PHY.

Thanks,

Vibhu

In the previous message I wrote:

"I see the DP83848 emitting fast link pulses on the Ethernet side."

Not sure if I can check the power consumption. Will think about how to do this.

Toshi

There are link pulses.

I cannot check the current consumption of the device.

Toshi

I see 1.74 volts on PFBOUT.

This seems like an odd voltage.

Is this correct?

Toshi

Hello Toshi,

Sorry for the late response. The 1.74 V on PFBOUT is okay. This should be around ~1.8 V.

Please check the following, and if not resolved share the schematic with me:

1. Is the MDIO pull-up correct? This device requires a 1.5k-ohm pull-up
2. Address strapping: double check the address strapping and ensure you are trying to communicate with the right address
3. Let me know if your oscillator meets the datasheet requirement: 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source
4. Are there any other PHYs in the system if so do they have any pull-ups on MDIO/MDC?

Thanks,

Vibhu

1. MDIO has a pull-up resistor, yes.

2. Address strapping is left as default.

3. Oscillator is 50 Mhz +-50ppm.

4. This is the only Ethernet PHY on the board.

Attached is the Ethernet schematic.

Attached is the board layout for the Ethernet section.

Board is four layers, top layer is red, layer 2 is ground, layer 3 is 3.3V, bottom layer is green.

Good to hear, I will be closing this issue.