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DS90UB954-Q1: DS90UB954: with DS90UB933 RAW10 setting

Steven He92
Expert 2125 points
Part Number: DS90UB954-Q1

Dear Sir,

My customer would use DS90UB933/ DS90UB954 RAW10 setting.

Please you kindly review below setting & give us advise.

for DS90UB933:

   - Adjust Mode resister value by internal or external PCLK

   - 0x05[2:0]=1

   - 0x14[2:1]=01

for DS90UB954

   - Adjust Mode resister value by RAW10

  - 0x70[7:6] & [5:0]

   - 0x6D[1:0]=11

   - 0x7C[7:6]=00

Thanks!

Steven

  • 0
    TI__Genius 11340 points

    Hi Steven,

    To put 954 in backwards compatibility mode, please check the following:

    • On 954:
    • Check Mode Pin to make sure it's in RAW mode:

     

    • RAW12 LF: 12-bits DATA + 2 SYNC bits
    • Input PCLK range of 25MHz to 50MHz
    • RAW12 HF: 12-bits DATA + 2 SYNC bits
    • Input PCLK range of 37.5MHz to 100MHz
    • Line rate = FPD3_PCLK x 2/3 x 28
    • RAW10: 10-bits DATA + 2 SYNC bits
    • Input PCLK range of 50MHz to 100MHz
    • Line rate: FPD3_PCLK/2 * 28
    • Check register 0x58 for back channel frequency:

     

    • Check AC coupling caps:

    • Check PoC Network:

     

    • Verify FV and LV signal timing
    • FrameValid (FV) = VSYNC
    • LineValid (LV) = HSYNC
    • FV must be high for a minimum number of FPD clock period (FV_MIN_TIME) prior to LV high:

    • If this requirement not met, sometimes first line is discarded, and last line becomes garbage