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Original question:

DP83867IS: DP83867ISRGZR:Power Sequencing in three supply mode

DP83867IS: DP83867IS:Power sequencing

Divy
Intellectual 380 points
Part Number: DP83867IS


Hi,

I am planning to connect the DP83867IS in 2 supply mode VDDIO> 1.8V , VDDA2P5> 2.5V and VDD1P1> 1V

As per datasheet no sequencing of supply is required. In the design sequencing followed is 1.8V> 2.5V> 1V

Is ther any ramp time requirements to to followed for the power rails.

Thanks,

Divy

  • 0
    TI__Mastermind 26320 points

    Hi Divya,

    POR requirements as shared in timing diagrams:

    1. Clock shall be available prior to power ramp

    2. Max difference two supply ramp shall be less than POR time of 200ms.

    Regards,

    Geet Modi

  • 0 in reply to Geet Modi
    Intellectual 380 points

    Hi Geet,

    I need more clarity on the below statement

     Clock shall be available prior to power ramp

    In the timing diagram shown in datasheet XI clock should be available before VDD supply rail ramps up.

    Before VDD means I understand XI clock should be available before final VDD supply rail ramps up. Please clarify.

    Sequencing we follow is 1.8V,  2.5V,1 V.  and Clock appears with 1.8V with a delay and before 2.5V and 1.2V.

    Thanks,

    Divy

  • 0 in reply to Divy
    TI__Mastermind 26320 points

    Before VDD means I understand XI clock should be available before final VDD supply rail ramps up. Please clarify.

    Yes this is correct.