I have a DS90UB953TRHBRQ1 Serializer moving MIPI data down to a DS90UB954TRGZRQ1. I need to pass an single channel I2S signal down three of the IO ports. I will be moving a single channel of 48Khz sampled data along with the Sclk and LRclk.
Will the ‘953 support this?
My thought is that I have 48khz audio which means my SCLK and 24 bits of audio data are moving at just over 3Mhz. The video path is moving way above that.... I read where the latency of forward channel GPIO inputs (moving from 953 to 954) was on the order of 130ns. This is roughly 7.6Mhz... So, If I can move the resulting ‘954 GPIO outputs to a FPGA that can resample at 140Mhz I think I'm fine...
Can you comment on this also?
