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DS90UB964-Q1: 1. question about the minimum power rise time; 2. MIPI test--two items failed

Sherry Liang
Genius 10255 points
Part Number: DS90UB964-Q1

Dear team,

1. The minimum rise time is 0.2ms as below, but the customer's design only has 0.15ms. What is the bad influence?

2. below is the customer's MIPI test report, there are two items failed. Do you have any suggestion to reduce these two parameters?

Thanks & Best Regards,

Sherry

  • 0
    TI__Guru** 103215 points

    Hello Sherry,

    For the power sequence all datasheet recommendations should be followed. If they are not, then we can not guarantee the device performance or potential problems which could occur.

    For the MIPI test, what data rate is being used?

    Best Regards,

    Casey

  • 0 in reply to Casey McCrea
    TI__Genius 10255 points

    Hi Casey,

    For the MIPI test, the data rate is 800Mbps.

    Thanks & Best Regards,

    Sherry

  • 0 in reply to Sherry Liang
    TI__Guru** 103215 points

    Hello Sherry,

    Can you please confirm that the test setup for MIPI compliance uses proper high speed connections? Is it possible to get a picture of the test setup for the signal connections?

    Thanks,

    Casey

  • 0 in reply to Casey McCrea
    TI__Genius 10255 points

    Hi Casey,

    The high speed connections, you mean below picture? The customer doesn't have such connection, their connections are similar with the second picture

    Before I asked you about 962's test about this same parameter. You said the connection is not correct. Could you please help explain these two parameters and why this connection will impact these two parameters? Maybe we don’t understand the two parameters correctly.

    Thanks & Best Regards,

    Sherry

  • 0 in reply to Sherry Liang
    TI__Mastermind 30515 points

    Sherry,

    For this issue, we think we have replied it before, pls check the test condition to be aligned with MIPI compliance test request. TI had validated the CSI2 in the 3rd party, and no issue is reported.

    Also, if your customer believed above test result from the test setup is correct, you can try the CSI2 indirect analog register 0x44 (Ths-pre) and 0x47 (Ths-exit) to set the timing parameter manually.

    7 this highest bit means: override is enabled if it is set as 1b'1.
    6:0 HS_PREP / HS_EXIT values