Hi ,
As per datasheet timing diagram
Clock shall be available prior to power ramp
In the timing diagram shown in datasheet XI clock should be available before VDD supply rail ramps up.
There are 3 VDD rails 1.8V, 2.5V,1 V. We use two supply configuration with VDDIO of 1.8V
Before VDD means I understand XI clock should be available before final VDD supply rail ramps up. Please clarify.
Thanks,
Divy
