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SN65DP159: Operation Timing

Y.Ottey
Mastermind 6145 points
Part Number: SN65DP159

Dear all,

I would like to ask 2 questions about operation timing.

The contents written as meaning at td1 in the table below are “VDD / VCC stable before VCC / VDD”.

What does "stable" as used here mean in the state of VCC or VDD?

(For example, when the voltage has risen to 90% of VCC or VDD, or when VCC or VDD has risen and stabilized)

Also, in the above table, can td1 and VDD_ramp (VCC_ramp) parameters be considered to indicate the part in the figure below?

Best Regards,

Y.Ottey

  • 0
    TI__Mastermind 35130 points

    Hi Y.Ottey,

    Stable means it's flat at its operating voltage and no longer rising. Figure 22 in the datasheet illustrates this timing.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Mastermind 6145 points

    Dear I.K.

    Thank you for your reply.

    I would like to ask more question.

    If VCC_ramp and VDD_ramp are 100ms, it is difficult to confirm that td1 is within 200μs. (With an oscilloscope, etc.)

    How can I check this?

    If VCC_ramp and VDD_ramp are 100ms, is td1 required to be within 200μs?

    (Can the td1 range described in the data sheet be applied in this case?)

    Regards,

    Y.Ottey

  • 0 in reply to Y.Ottey
    TI__Mastermind 35130 points

    Hi Y.Ottey,

    You can avoid the timing requirements by keeping OE low until Vcc/Vcc are stable. Namely, you should just ensure that OE is pulled high only after both Vdd and Vcc have been stable high for at least 100us. Td1 doesn't matter in this case, you just need to meet td2. 

    Regards,

    I.K.