This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB926Q-Q1: Status pin question

Part Number: DS90UB926Q-Q1

Hello,

I have the following question below for Texas Instruments PN DS90UB926QSQX/NOPB.  Can you help me find an answer?

There are two status output pins on the DS90UB926QSQX/NOPB deserializer IC that are stated in the specification as shown in the screen-shot below.  I have a verification test to monitor each output in an overnight run by using an oscilloscope to probe each signal and trigger on the falling-edge.  If the scope triggers, this would indicate an error and test failure.  However, before I run this test I was hoping you could do a sanity check for me.  I read the specification and my interpretation is that these outputs are only active during BIST mode.  However, the definition doesn’t state that in the Status Pin Function section of the datasheet (pg7) from the specification so I am confused.  I am wondering if you can confirm if the STATUS pins PASS and LOCK are active during normal running mode, or just in BIST mode?

 Thanks,

Adam

  • Hello Adam,

    For DS90UB926Q-Q1, I believe the PASS pin is used only for BIST mode operation however we can check the operation in normal mode to confirm it. It should only take 1-2 business days to double check it. 

    Best Regards,

    Casey 

  • Thanks Casey,

    Also another separate issue I am having has come up.  I am probing the PASS status output pin over the course of the day.  It’s logic high output, but every occasionally my scope triggers (Setup for falling-edge trigger) and I observe a burst on the PASS output signal.  The pin isn’t connected to anywhere on my PCA.  It is just a functional test point so no other external source should be causing it.  I’ve pasted a screen-shot below for your review.  Will you please shed some light if you can?  I am running the deserializer in normal mode here, not BIST mode to be clear.

     

     screenshot.docx

  • Hi Adam,

    I wanted to confirm that PASS is used just for BIST. In terms of your other question, do you have some power source nearby? I'm seeing about a 15V swing there and I don't see how our part could generate that high of a voltage. That pin may be coupling to some power or noise source.

    Regards,
    Mandeep Singh

  • Hello Adam,

    Do you have any updates or any further questions?

    Regards,
    Mandeep Singh

  • Hello Mandeep,

    Is using the PASS pin output worth checking if the part is put into BIST mode in order to check if normal LVDS data is being received w/o error?  My understanding of BIST mode is that it’s an internal test so I’m wondering if it’s going to be a valid test on external LVDS signals that are sent into the IC.

     As far as the Bursts are concerned.  The PCB is powered by +5VDC.  The other voltage on the PCB is +3.3V.  The PCB design doesn’t have +15V on this board.  The +5V switcher that is on a different PCB has an input voltage of +15V.  I wouldn’t expect the +15V to make its way through the switcher when it has Pi filtering and ferrite beads at the +5V switcher output.  In any case, you don’t observe any kind of bursts (Of any voltage magnitude) on these pins on test boards?

    Thanks!

    Adam

  • Hi Adam,

    Your understanding is correct in regards to BIST, it would not give an indication of the LVDS data quality, so if you are trying to evaluate that, it will not be worthwhile with that pin. If you want to check the signal quality, it's better to look at the CMLOUT pins and you can measure whether the Eye width and height meets the spec.

    We don't observe this type of swing in our testing. If possible in your set-up, I'd recommend isolating the Ser and Des from the rest of the system and see if there's something that's still coupling and causing it to fall. If you have EVMs, that could make it easier and you can see if the issue is repeatable on the EVMs as well.

    Regards,

    Mandeep Singh