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DP83867IRPAP-EVM: Not working when trying to force link at 100Mbs.

user6199499
Prodigy 100 points
Part Number: DP83867IRPAP-EVM

Hello,

I've tried the board with the Auto-Enable board and I'm receiving signals correctly to the oscilloscope. When I try to force the board to work at 100Mbs the Rx stops receiving but the Tx keeps working.

In the Rx side the clock is at 25MHz, the enable is always off, and two data signals are always on. Setting the trigger at one of the data signals I can see that in some moment of time the clock stops working and then it resets to 2.5MHz and after 4 cycles to 25MHz again. 

To force 100Mbs i've changed the following register using MDI:

0x0000 0x2100

I've also tried to force link changing the following:

0x0010 0xD448

The Tx side works properly but the signals are not correctly aligned between them, but that would be probably a problem of overshooting/undershooting or maybe noise, I will check with a non-digital probe later on, but first I'm trying to solve the problem with the Rx side.

I will attach three images, two of the Rx clock turning off and then on, and the final one of the Tx side. For Rx: D8 is RXCLK, D9 is RX_CTL and D10:D13 are RXD. For Tx: D0 is TXCLK, D1 is TX_CTL and D4:D2 are TXD. 

Thanks you.

 

  • 0
    Prodigy 100 points

    I want to add something to the previously said. When I say that it work with the Auto-Enable On I mean it works at 1000Mbs, I've just tried to advertise it as 100Mbs and It doesn't work. It happens the same as before.

  • 0 in reply to user6199499
    TI__Mastermind 23675 points

    Hi,

    Can you check if you are enabling mirror mode and/or auto-mdix?

    Please send us a register dump from 0x0 to 0x1F.

  • 0 in reply to Ross Pimentel
    Prodigy 100 points

    I've checked the mirror mode and auto-mdix and it seems that everything is correct here. I've tried with the MDI/MDI-X in automatic and manual and with both types of cables.

    About the register dump, I don't have and USB to MDIO board to manage the registers, I'm using a custom IP core and an FPGA, the problem is that the core is not designed to read more than one register without recompiling. I will modify the block to be able to do it. Please don't close the topic, I will contact you as soon as I have the register values. I will have it between this week and the next one.

    Thanks.

  • 0 in reply to Ross Pimentel
    Prodigy 100 points 
    0x0000 0x2100
0x0001 0x7949
0x0002 0x2000
0x0003 0xA231
0x0004 0x01E1
0x0005 0x0000
0x0006 0x0064
0x0007 0x2001
0x0008 0x0000
0x0009 0x3000
0x000A 0x4000
0x000B 0x0000
0x000C 0x0000
0x000D 0x401F
0x000E 0x0000
0x000F 0x3000
0x0010 0x5048
0x0011 0x6B02
0x0012 0x0000
0x0013 0x0000
0x0014 0x29C7
0x0015 0x0000
0x0016 0x0000
0x0017 0x0000
0x0018 0x6150
0x0019 0x4444
0x001A 0x0002
0x001B 0x0000
0x001C 0x0000
0x001D 0x0000
0x001E 0x0002
0x001F 0x0000

0x0031 0x0B0