We are troubleshooting a new board bring up with a DP83867E connected to Xilinx Ultrascale MPSoC GEM1, where we cannot establish a connection with a windows PC.
We've dumped all of the PHY registers on both a reference ZCU102 and our new board which brought to our attention that STRAP_STS2 and CFG4 both have bits set to 1 that are reserved, RO, and should be defaulted to 1. We're wondering if these bits can shed any light on what's wrong.
CFG4 (address 0x0031) is 0x10b0 at startup and STRAP_STS2 (address 0x006f) is 0x100 at startup. Does this give any indication of what may be wrong with our configuration?
