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DP83867IR: 10-Mbps and 100-Mbps Transmit Timing under RGMII MAC Interface Mode

Koshi Ninomiya
Expert 5425 points
Part Number: DP83867IR

Hi Team,

My customer is evaluating the DP83867IRRGZ (RGMII), and they have some questions as below.

Q1: 100-Mbps Transmit Timing under RGMII MAC Interface Mode:
          Which TX_CLK edge, rising edge or falling edge, is the TDX[3:0] data latched on?

          If the Bit-1 of RGMII Control Register (RGMIICTL, 0x0032) is set "1", RGMII transmit clock is shifted, under 100-Mbps mode, how much RGMII Transmit Clock Delay is allowable?

Q2: 10-Mbps Transmit Timing under RGMII MAC Interface Mode:
          Which TX_CLK edge, rising edge or falling edge, is the TXD[3:0] data latched on?

         If the Bit-1 of RGMII Control Register (RGMIICTL, 0x0032) is set "1", RGMII transmit clock is shifted, under 10-Mbps mode, how much RGMII Transmit Clock Delay is allowable?

Thank you.

Best Regards,

Koshi Ninomiya