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TLK2501: Maximum allowed jitter

Nir Flysher
Expert 3287 points
Part Number: TLK2501

Dear Team,

My customer is working with the TLK2501 for the past 10 years.

In recent design they have an issue regarding PLL lock signal.

They are connecting pin # 41 – RX_CLK to a MMCM input of ARTIX7 FPGA from XILINX.

 

From time to time, when we power the system at minus 30 degC , the MMCM reports that the PLL is not locked, and after a few seconds it is locked again.

 

We suspect that this is a jitter issue. The maximum allowed jitter at the FPGA MMCM input is 80 psec.

I don’t see at the TLK2501 datasheet  the maximum jitter on the TLK2501 RX_CLK output (including all temperature scale)

 

Can you advise ?

Regards,

Nir

  • 0
    TI__Mastermind 19225 points

    Rx_CLK is output clock that is synchronized to RXD, RX_ER, RX_DV/LOS. RX_CLK is the recovered serial data rate clock divided by 20. As this signal is pretty low speed (~75 MHz) jitter should be negligible. Similar to spec for GTX_CLK, the RX_CLK jitter peak-to-peak should not exceed 40ps.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    TI__Expert 3287 points

    Hi Rodrigo,

    Thanks for the quick response.

    Please see additional questions regarding this topic.

    At our application, we are using the TLK2501 only as De-serializer. (Rx only)

    We are connecting pin # 41 – RX_CLK to a MMCM input of ARTIX7 FPGA from XILINX.

    From time to time, when we power up the system, at minus 30 deg , the MMCM reports that the PLL is not locked, and after a 2-3 seconds it is locked again.

     

    At our application, at this time, there  is no video signal at the differential video inputs – pins # 53,54 (DINRXP,N). the video arrives ~30 seconds after power up,

    But we see a clock signal at pin 41 (Rx_Clk signal) at power up, with no video at the TLK2501 inputs.

    The clock frequency is 125Mhz – same clock that we connect to pin 8 – GTX CLK.

     

    Q:

    1. why do we see a clock signal at  RxClk pin, without video at the input?

        As I see at the datasheet – the clock is extracted from the video

    2. until video arrives – is it a valid clock? Can I lock the PLL from this clock until the video arrives?

    3. is there a difference at the RxClk signal – with and without a video at the TLK2501 inputs?

     

    Best Regards,

    Nir

  • 0 in reply to Nir Flysher
    TI__Mastermind 19225 points

    Hi,

    Can you confirm the status of the following TLK pins during the period where there is no input video data present but there is RX_CLK signal output?

    • RX_ER
    • RX_DV/LOS
    • LCKREFN

    Thanks,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    TI__Guru** 119425 points

    Nir:

       Can you reply Rodrigo's question?

    Regards,

    Brian