TS3USB221A: TS3USB221A

you mean PC can't find CPU device? D1+/D- does in high impedance at that condition.

Hi,

When testing is there anything connected to DP and DM? If multiple devices are connected to the same bus then USB 2 HS termination may be incorrect, as seen by the Host. (i.e. Multiple terminations in parallel.)

1.the PC host can not find the CPU device while the switch is connect the 2D output and the input signal.

2. does that mean while the 1D+&1D-  traces are in high impedance condition, the differential traces are held and stopped been checked by the PC host? 

Hi  Malik,

When testing I didnot connect any device to the switch signal input(DM & DP). 

And I had set OE=Low and S=High which means the 1D output and the switch input are not connected. right?

And it seems that while the 2D output and the switch are connected,the condition of 1D output affects the CPU device to be checked by the PC host. It confuses me because I dont know why this happens.

Hi,

Could you capture DP and DM in the failure state? This will help understand what is happening to the USB 2 enumeration process when both devices should be connected. I recommend capturing when the CPU turning on.

Hi  Malik,

Thanks for your suggestions.

And here is a new issue.

1)Technically we can connect 2 switch in series. Correct?

2)When I set the two chips' S=LOW,I can capture the same signal at TP1 and TP2 at the same time. So I think the whole DP/DM traces are connected. And behind the TP2(L4), its just the CPU chip. However the PC host still can not identify my device as a virtual COM.

But  if I remove the U10 chip, and connect my device to PC host through the J1 connector. The PC host can check my device good. 

So it seems the switch chips have some side effects on the system. Can you offer some ideas?