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DP83867IS: SGMII to SGMII

Part Number: DP83867IS
Other Parts Discussed in Thread: DP83867ERGZ-S-EVM, , DP83869, DP83869HM

Hi again,

(this is a followup of https://e2e.ti.com/support/interface/f/138/p/764147/2824692. Thanks for the first answer there & sorry for not responding.)

We habe a module with [Linux-SOM => Ethernet => DP83867IS => SGMII => connector] and a 3rd party host [connector => SGMII => unknown]. In production and development we want to be independant of the 3rd party host (There are several reasons for this). Our idea is to use a second DP83867 and create a bridge like this: [Linux-SOM => Ethernet => DP83867IS => SGMII => connector] [connector => SGMII => DP83867ERGZ-S-EVM => Ethernet => RJ45 => cable => Laptop/Switch/"house ethernet"].

Here are registers from our module (where Ethernet between SOM and DP83967 should be active, but apparently isn't)

Register 0000 is: 1140
Register 0001 is: 796D
Register 0002 is: 2000
Register 0003 is: A231
Register 0004 is: 01E1
Register 0005 is: C5E1
Register 0006 is: 006F
Register 0007 is: 2001
Register 0008 is: 6801
Register 0009 is: 0300

For comparison, the registers of the DP83867ERGZ-S-EVM, connected to a Ethernet-switch:

Register 0000 is: 1140
Register 0001 is: 796D
Register 0002 is: 2000
Register 0003 is: A231
Register 0004 is: 0181
Register 0005 is: 4DE1
Register 0006 is: 0067
Register 0007 is: 2001
Register 0008 is: 0000
Register 0009 is: 0300

Questions:

  1. The link status refers to the (Ethernet) PHY link, not the SGMII link, correct?
  2. Is the approach of connecting two DP83867 via SGMII the right approach anyway? Crossing So and SI pairs?
  3. Any hints of debugging what's wrong/different on the module's DP, compared to the EVM?

  • Hello Kajetan,

    Yes, the link status refers to the (Ethernet) PHY link.

    This application may cause issues as the SGMII also has an auto-negotiation process where one PHY would be required to act as the slave. In the current case both your PHYs are acting as master and are unable to resolve this.

    Here is something you can try:

    "The SGMII Auto-Negotiation process can be disabled and the SGMII speed mode can be forced to the MDI resolved speed. The SGMII forced speed mode can be enabled with the MDI auto-negotiation or MDI manual speed mode. SGMII Auto-Negotiation can be disabled through the SGMII_AUTONEG_EN register bit in the CFG2 register (address 0x0014)."

    Another way to go about this problem is using a DP83869 in RGMII-SGMII bridge mode:

     [Linux-SOM => Ethernet => DP83867IS => SGMII => connector] [connector => SGMII => DP83869HM Bridge => RGMII => DP83867ERGZ-S-EVM => Ethernet => RJ45 => cable => Laptop/Switch/"house ethernet"]

    Thanks,

    Vibhu

  • Hi Vibhu,

    thanks for the fast answer.

    Sadly clearing the SGMII_AUTONEG_EN bit did not lead to the intended bahaviour right away. I will continue to dig into this on Monday with tho USB-MDIO tools.

    Just to be on the save side, can you please review my DP83867 to DP83867 cabeling?

    GND <-> GND

    SI_p <-> SO_p

    SI_n <-> SO_n

    SO_p <-> SI_p

    SO_n <-> SI_n

  • Hello Kajetan,

    Sorry if my previous response wasn't clear.

    In addition to disabling SGMII_AUTONEG_EN, you also need to force both the PHYs into a certain mode after disabling the PHYs' auto-negotiations. Use register 0x0000 bits 13, 12 and 8 for this.

    Good luck with the rest of the debug.

    Thanks,

    Vibhu

  • Hello Vibhu,

    thanks, I think I am still missing something. The link is Ethernet-connection is shown as 1000MBit on my laptop after full reset of the chip. After writing the registers I loose the Ethernet/MDI link. Doing this to both sides also does not help.

    Here is my routine (debug-read, write registers to disable negotiation, reset chip without registers, debug-read again)

    register 0000 read  0x1140
    register 0001 read  0x796D
    register 0002 read  0x2000
    register 0003 read  0xA231
    register 0004 read  0x0181
    register 0005 read  0xCDE1
    register 0006 read  0x006F
    register 0007 read  0x2001
    register 0008 read  0x4006
    register 0009 read  0x0300
    register 000a read  0x7800
    register 000b read  0x0000
    register 000c read  0x0000
    register 000d read  0x0000
    register 000e read  0x0000
    register 000f read  0x3000
    register 0010 read  0x5848
    register 0011 read  0xBC02
    register 0012 read  0x0000
    register 0013 read  0x1C42
    register 0014 read  0x29C7

    register 0000 read  0x1140
    register 0000 write 0x2300
    register 0000 read  0x2100
    register 0014 read  0x29C7
    register 0014 write 0x2907
    register 0014 read  0x2907
    register 001f write 0x4000 (reset chip without registers)

    register 0000 read  0x2100
    register 0001 read  0x7949
    register 0002 read  0x2000
    register 0003 read  0xA231
    register 0004 read  0x0181
    register 0005 read  0x0000
    register 0006 read  0x0064
    register 0007 read  0x2001
    register 0008 read  0x0000
    register 0009 read  0x0300
    register 000a read  0x0000
    register 000b read  0x0000
    register 000c read  0x0000
    register 000d read  0x0000
    register 000e read  0x0000
    register 000f read  0x3000
    register 0010 read  0x5848
    register 0011 read  0x6B02
    register 0012 read  0x0000
    register 0013 read  0x0440
    register 0014 read  0x2907


    register 0000 : 0x2100
            bit[15]  0 RESET
            bit[14]  0 LOOPBACK
            bit[13]  1 SPEED SELECTION LSB
            bit[12]  0 AUTO-NEGOTIATION ENABLE
            bit[11]  0 POWER DOWN
            bit[10]  0 ISOLATE
            bit[ 9]  0 RESTART AUTO-NEGOTIATION
            bit[ 8]  1 DUPLEX MODE
            bit[ 7]  0 COLLISION TEST
            bit[ 6]  0 SPEED SELECTION MSB
            bit[ 5]  0 reserved
            bit[ 4]  0 reserved
            bit[ 3]  0 reserved
            bit[ 2]  0 reserved
            bit[ 1]  0 reserved
            bit[ 0]  0 reserved


    register 0001 : 0x7949
            bit[15]  0 100Base-T4
            bit[14]  1 100BASE-TX FULL DUPLEX
            bit[13]  1 100BASE-TX HALF DUPLEX
            bit[12]  1  10BASE-Te FULL DUPLEX
            bit[11]  1  10BASE-Te HALF DUPLEX
            bit[10]  0 100BASE-T2 FULL DUPLEX
            bit[ 9]  0 100BASE-T2 HALF DUPLEX
            bit[ 8]  1 EXTENDED STATUS
            bit[ 7]  0 RESERVED
            bit[ 6]  1 MF PREAMBLE SUPPRESSION
            bit[ 5]  0 AUTO-NEGOTIATION COMPLETE
            bit[ 4]  0 REMOTE FAULT
            bit[ 3]  1 AUTO-NEGOTIATION ABILITY
            bit[ 2]  0 LINK STATUS
            bit[ 1]  0 JABBER DETECT
            bit[ 0]  1 EXTENDED CAPABILITY


    register 0014 : 0x2907
            bit[15]  0 reserved
            bit[14]  0 reserved
            bit[13]  1 INTERRUPT_POLARITY
            bit[12]  0 reserved
            bit[11]  1 SPEED_OPT_ATTEMPT_CNT
            bit[10]  0 SPEED_OPT_ATTEMPT_CNT
            bit[ 9]  0 SPEED_OPT_EN
            bit[ 8]  1 SPEED_OPT_ENHANCED_EN
            bit[ 7]  0 SGMII_AUTONEG_EN
            bit[ 6]  0 SPEED_OPT_10M_EN
            bit[ 5]  0 reserved
            bit[ 4]  0 reserved
            bit[ 3]  0 reserved
            bit[ 2]  1 reserved
            bit[ 1]  1 reserved
            bit[ 0]  1 reserved

    Any ideas?

    Best regards,

    Kajetan

  • Hello Katejan,

    When you read the link status please wait 10 s after you configure the PHY.

    If that doesn't work also try setting 0x0014 to 0010 1011 0100 0111 (0x2947).

    Thanks,

    Vibhu