Part Number: DS90UH948-Q1
Hi team,
I would like to know the definition of the Tjcc spec at 2-lane FPD-Link III input, single OpenLDI Output in UH948 datasheet.
Is that the total cycle to cycle jitter on oLDI LVDS clock out?
I am now trying to calculate the minimum channel to channel skew margin(RSKM) between the timing controller oLDI input.
Should I simply subtract Tjcc/2(consider RSLM left and right) from the RSKM spec of the timing controller's oLDI input?
regards,
