LMH1218: Out 0 Signal Degrades After CDR Reset

Hello Nasser,

Thanks for the reply.  Here are the images of what  I am seeing.  First image is after POR, second is after CDR reset.

We do have SMbus access and have been looking at the EOM.  I will step through and monitor where the problem occurs.

Do you recommend using the procedure on page 14 to determine the correct CTLE setting?  I have <1" of FR4.  Running EOM the eye opens up with Reg 0x03 manually set to 00.  Thanks.

Hi Dan,

Less than 1" trace is very short. Please use 0x00 settings. Device has some residual gain. It's a good idea to have 4-5 inches of trace before the device input.

Regards,, Nasser

Hi Nasser,

I performed the initialization sequence per page 4 of the LMH1218 Programming Guide, Revised June 2018.  My device fails when I reset the CDR.  I have compared the register values looking for a difference between resetting the CDR and a POR.  Nothing jumps out at me.

For this go around, I will not be able to reset the CDR, until I can come up with a better solution.

Hi Nasser,

I receive the same result when performing the above sequence.  The alignment jitter increases as I captured in the previous pictures.  I will use the part without resetting the CDR.  Thanks.

Hello Nasser,

You mentioned above recommending 4-5" of trace length feeding IN0 of the LMH1218.  My FR4 lengths are between 0.75 and 1.25".  I am still having issues at 12G with CRC errors, but have the alignment jitter at approx. 0.22UI max.  What is the min. FR4 trace you would be comfortable with?

Thanks.

Hi Dan,

If you put the CDR is bypass or CDR bypass, do you still get CRC error?

Regards,, Nasser

Hello Nasser,

I would like to try that, but cannot find the register to put CDR in bypass.  Can you send me instructions?

Is there a newer programmer's guide than SNLU174B, revised June 2018?

Thanks.

Hello Nasser,

I believe the documentation describes CDR bypass mode as OUT0 RAW Data?  If so, that did not resolve the issue.  The alignment jitter increased beyond 0.3UI and I received many more CRC errors than when the CDR is enabled.

Hi Dan,

Yes documentation calls this RAW mode. Reg 0x1C[3:2]=2'b11 enables raw mode.

We asked for raw mode since we were worried if the short trace on your 50-ohm input may be over-equalized causing extra jitter on CDR . But this does not seem to be the case(based on your experiment above). 

It is possible maybe the device - on the receiving side of the LMH1218 output -  jitter tolerance is low to the point it is getting bit error. There are two things that you can try:

1). Reduce clock jitter or jitter on the FPGA or the device driving LMH1218 50-ohm input.

2). You can try changing reg 0x9B and 0x9C both to a lower value like 0x01(default = 0x04). This typically tightens the loop filter bandwidth and reduces the output jitter.

Regards,, Nasser

Hi Nasser,

We have written 0x01 to reg 9B and 9C and see a reduction in alignment jitter, but still receive CRC errors.  It could be that my source which is driving the LMH1218 has too much jitter on it.

What is curious to us is that we have a different design which uses the same source device, but feeds the LMH1219 and do not see this issue (it is feeding IN 1 of the LMH1219).  Are the input structures and EQ gain the same between the LMH1218 (IN 0) and LMH1219 (IN 1)?

We are in the middle of relaying out the PCB which uses the LMH1218, and we may need to design in a different part if we cannot get the LMH1218 to behave like the LMH1219.

Thanks.

Hi Dan,

LMH1218 and LMH1219 50-ohm inputs use the same IP/structure and performance is the same.

Is it possible  to take LMH1218 50-ohm output - instead of 75-ohm output - check CRC error on this output? This way we isolate media dependency.

Regards,, Nasser

Hi Nasser,

Thank you for following up, as we have decided to focus on why resetting the CDR on the LMH1218 caused alignment jitter to increase by 0.15UI, whereas resetting the LMH1219 does not cause a problem.  Since my traces are so short (<1"), I tried enabling EQ override in the LMH1218 (2D 08 08), but that did not change my result.  Up until yesterday, we were not writing to reg 2D (or 3F in the LMH1219), so even though reg 0x03 and 0x52 were set to 0, the parts were still in adaptive mode.

A colleague who is using the DS125DF1610 said he has to write to the registers, reset the CDR, then write to the same registers again for his settings to take effect.  I am going to try that with the LMH128.