Dear sir/ madam,
I am using DP83869HM chip to bring up the Ethernet setup in MII mode. Register configuration for MII-to-Copper (10Base-Te/100Base-TX) mode is done as follows: 1. BMCR (Address = 0x0) with 0x2100 - to select speed of 100mbps. 2. GEN_CFG1 Register (Address = 0x9) with 0x0000 - disabling advertising 1000mbps. 3. GEN_CFG2 Register (Address = 0x14) with 0x29d7 - selecting the frequency of transmit clock to 25MHz(100mbps). 4. OP_MODE_DECODE Register (Address = 0x1DF) with 0x0060 - to set MII mode. 5. GEN_CFG4 Register (Address = 0x1E) ¬¬¬¬¬¬¬ with 0x0212 - enabling 9th bit CFG_ROBUST_AMDIX_EN. Probed both transmit and receive clocks which are transmitted by PHY in MII mode and found that they are 25Mhz. Then we have sent Packets from PC to FPGA and found that FPGA is not sending reply packets. Probed and found that receive data of FPGA is not toggling that means request packets sent from PC are not received by FPGA So please check above mentioned register setting and let me know if Iam missing something
