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DP83869HM: Design Review

Jeong Jaemin
Prodigy 25 points
Part Number: DP83869HM

* Config

- Configure the media converter using the DP83869HM device.

- The front end uses Giga-bit RJ45 Copper SFP module.(1000BASE-FX)

- Rear end uses RJ45 connector.(1000BASE-TX)

* Problem

- The network connection status of the front and back stages is confirmed by the computer, but when the ping test is performed, the result is displayed as a failure.

* Requirements

- Request for a design review and response to the attached schematic.

Thanks:)

  • 0
    TI__Genius 11900 points

    Hello Jeong,

    Please first take a look at the attached documents and if further help is required let me know and I can review the schematic for you.

    http://www.ti.com/lit/an/snla318/snla318.pdf: this document provides information regarding the different modes this PHY can be used in along with strap configurations. Please double check that all your straps match with the straps listed in the selected media converter mode.

    https://www.ti.com/lit/df/snlr042/snlr042.pdf: this is the evaluation modules schematic, you can use this as a reference schematic.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 25 points

    Hello Vibhu,

    1. checking the strap data I received and found that the circuit I built has both LED1 and LED2 connected to zero.

    Q) Looking at the datasheet, I think the LED1, 2 configuration is the difference between 100/1000 or 1000. 

         In the data sheet, the auto-negotiation range changes as LED1 and LED2 are connected to 0 or 1, is there a difference between the two?

    2. After comparing the reference circuit and my circuit, it seems that the clock and reset configurations are slightly different.

    Q) The clock consists of a 25MHz oscillator and the reset consists of an external chip and a pull-up resistor.

         Is there anything in the current configuration that needs to be supplemented?

    * I'll attach my whole circuit if needed.

    Thanks:)

  • 0 in reply to Jeong Jaemin
    TI__Genius 11900 points

    Hello Jeong,

    1) There are a couple things to look at for configuration:

    To answer your question LED1 and LED 2 configure the ANEGSEL_0 and ANEGSEL_1. When both of these are 0, auto-neg advertises both 1000 and 100. When set to 1, auto-neg only advertises 1000. In both cases Auto-MDIX is enabled.

    Please also check to see if 0x01DF contains 0x0044 for 1000 Mbps and set 0x01EC to 0x1FFC.

    Additionally, confirm that the registers mentioned in "9.4.8.4 1000M Media Convertor Mode" of the datasheet are written as shown.

    This document may also help with your debug: https://www.ti.com/lit/an/snla305/snla305.pdf.

    2) As long as you meet the voltage and timing requirements for reset the method this pin is controlled should not be an issue.

    Please also share with me your system level block diagram so I have more clarity on how your PHY is setup. You mentioned that the network status is confirmed, can you elaborate on this? Is there a link?

    Thanks,

    Vibhu

  • 0 in reply to Jeong Jaemin
    TI__Genius 11900 points

    Hello Jeong,

    I was wondering what the status of this is debug was, please provide an update if further support is needed.

    Thanks,

    Vibhu