DS125DF410: Retimer 1.0625Gbps Speed Locking issue

Hi,

The DS125DF410 does not support 1.0625Gbps in retimed mode. However it can operate at 1.0625Gbps and meet standard requirements while set to CDR bypass mode. Alternatively the DS110DF410 may be used for this application. The DS110DF410 shares the same design as DS125DF410 and it is 100% pin-to-pin/footprint compatible. But the DS110DF410 supports data rate range of  8.5 to 11.3 Gbps plus divide by 2/4/8 Sub-rates. 8.5Gbps divided by eight is 1.0625Gbps.

Cordially,

Rodrigo Natal

HSSC Applications Engineer 

Hi Rodrigo Natal,

I have connected three DS125DF410 retimer with single I2C line with 4.7k pull up, but i am seeing glitches in the i2c SDA line.

Also I want to disable two retimer to debug the same I2C bus. May i know how to disable the two retimer.

Also I have connected 3.3V lvcmos 25MHz reference clock instead of 2.5V lvcmos (refer schematic in: https://e2e.ti.com/support/interface/f/138/t/830071). Does this will ref clock is creating the issue?

Waiting for your valuable reply..

Regards,Ananthesh

• I have connected three DS125DF410 retimer with single I2C line with 4.7k pull up, but i am seeing glitches in the i2c SDA line
  • Please confirm that each retimer has a unique I2C/SMBus Slave address
    
•      Also I want to disable two retimer to debug the same I2C bus. May i know how to disable the two retimer

• You may put the two retimers in reset via the READ_EN_N hard pin. When in SMBus Slave Mode (i.e. EN_SMB=1) if READ_En_N is asserted low, this causes the device to be held in reset (I2C state machine reset and register reset).

• Also I have connected 3.3V lvcmos 25MHz reference clock instead of 2.5V lvcmos (refer schematic)

• It's possible. I would recommend to switch to 2.5v LVCMOS device, to align with the TI retimer datasheet

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Hi Rodrigo Natal,

All the three Retimer having its own unique slave address based on ADDR[3:0] pin strap settings.

Can I get any example C code for the sequence to be followed to configure retimer at different data rates.

Regards,
Ananthesh

Hi Natal,

On the positive note, we are able to establish SMBUS communication with one of the I2C Slaves in the bus.
Issue/Fix: I2C transactions were not atomic, this might not be the acceptable in SMBUS, we did not Root-cause the issue and continued with our development.

We have read the Control/Shared Register Set. And able to read the Device ID which matches to the strap settings we have done. As per the section 7.5.1 in datasheet

After this we have configured the Channel Register set to match with the Timer Channel 0 (as per our schematics to which channel we are targetting)

After which we have done the below Configuration as per the guidelines to be set in the 7.4.4 Standards-Based Modes

The register configuration procedure is as follow:
1. Select the desired channel of the DS125DF410 by writing the appropriate value to register 0xff.
Ans: Value written: 0x04 for Channel 0

2. Set bits 5:4 of register 0x36 to a value of 2'b11 as described above to enable the 25 MHz reference clock.
Ans: This was set by default. Read and confirmed.

3. Write registers 0x2f with the correct values.
Ans: 0x26 is written to match Infiniband Mode to run at 2.5Gbps

4. Compute the expected PPM count values for Group 0 and Group 1 as described above.
Ans: PPM Values computed = 2800 x 10Gbps = 28000 = Hexa 3200 =Set MSb Result = (B200)Hexa.

5. Write the expected PPM count values into registers 0x60-0x63 as described above, setting bit 7 of both registers 0x61 and 0x63.
Ans: Values are written 0xb200 to both Group 1 & Group 2 Registers

6. Set the value 0xff into register 0x64 for an approximate PPM count tolerance of 1100-1400 PPM.
Ans: 0xFF is set to 0x64 register.

7. Reset the retimer CDR by setting and then clearing bits 3:2 of register 0x0a.
Ans: Bits are set to 1 and reseted to 0.

After all these Configuration also we are not able to see any output from the Retimer.
We have followed the Read-Modify-Write while targeting the Registers.
All transactions are atomic and the values configured and read back and verified.

Please provide some debug steps and guidelines.

HI,

You are configuring the retimer to lock to 10Gbps input data rate. What exact input signal data rate and data pattern are being implemented here?

Please note that if you already have set 0x2F = 0x26 then you do not need to program registers 0x60 through 0x63. I would suggest not to in this case. Setting 0x2F = 0x26 by itself configures the CDR for InfiniBand rates.

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Hi Natal,

We have advanced in the testing and below is the status.

We changed the data rate from the Transmitter to 2.5Gbps. and applied the above settings of 0x2F = 0x26 to incorporate to standard mode of infiniband Rates.

CDR Lock Status is Not Locked.

When we read the Channel register 0x02, it is toggling between 3 values - 0x00, 0x04, 0x05

As well the signal Detect is toggling continuously.

We tried to force the Signal Detect by Force but after forcing also the CDR Lock status will be toggling.

We have checked the channel at the input of Retimer and the data is prominent. Also it is around 700mV more than the Threshold set for Signal Detect of 70mV.

Regards,
Ananthesh

Hi,

Thanks for the evaluation update. Based on your observations I would recommend the following two experiments.

1. Try disabling each of the CDR lock qualifiers, then check whether the retimer channel is able to lock to your 2.5Gbps signal
   1. Disable Single Bit Transition (SBT) check -> Performed by setting 0x0C[3]=0
   2. Disable PPM check -> performed by setting 0x2F[2]=0
   3. Set the HEO/VEO lock thresholds to zero -> performed by setting 0x6A = 0x00
2. Try setting the retimer channel to CDR reference mode 0, and see whether the retimer channel is able to lock to your 2.5Gbps signal
   
   • This setting is performed by setting 0x36[5:4]=b00

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Hi Natal,

Thanks for your update, your suggestion helped us to root cause the issue.
Result of the earlier experiment was CDR was locking when SBT qulifier was disabled. after which we have tuned the TX Diff Swing from the Transceiver to achieve the CDR lock.

But we have moved to the next level of testing and we need your suggestion here.

Our final aim was for the data rate of 1.0625 Gbps, but the device selected 'DS125DF410' wont support the same because of the unavailable combination of VCO frequency & Divider values.
Hence we have moved to the new device : DS110DF410, we have got the same and mounted on the board, which support 8.5Gbps with divider value 8 gives 1.0625Gbps.

In this device we do not have standard-based mode for the datarate of 1.0625Gbps, Hence subrate settings has to be done for the same.

Can you send us the register configuration for the data rate of 1.0625Gbps.

Regards,
Ananthesh

Hi,

The following DS110DF410 channel registers configuration may be used for 1.0625Gbps operation.

0x60 = 0x80

0x61 = 0xAA

0x62 = 0x80

0x63 = 0xAA

0x64 = 0xFF

0x18 = 0x30

0x09 = 0x04

(CDR reset and release operation is recommended)

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Hi Natal,

I did the configuration as per your guidelines. Please find the below code snippet for reference.

Result is we are not able to detect the data at the Timer input and the CDR is not locking. As per your suggestion i have masked the CDR qualifiers to check what is causing the issue, but it is not giving stable value to see the cause. Is there any other configuration i am missing?

Regards,

Ananthesh

############### Code snippet #####################
//Write 0xff, val: 0x04 : Change control from Control Reg Set to Channel Reg Set,

//Read 0x36 : Check whether 25MHz clock is set [5:4] = 2'b11;

//Write 0x60, val: 0x80 : Set PPM Values
//Read 0x60 : To check whether the PPM values are set accordingly

//Write 0x61, val: 0xAA : Set PPM Values
//Read 0x61 : To check whether the PPM values are set accordingly

//Write 0x62, val: 0x80 : Set PPM Values
//Read 0x62 : To check whether the PPM values are set accordingly

//Write 0x63, val: 0xAA : Set PPM Values
//Read 0x63 : To check whether the PPM values are set accordingly

//Write 0x64, val: 0xFF : Set PPM Values
//Read 0x64 : To check whether the PPM values are set accordingly

//Write 0x18, val: 0x30 : Set PPM Values
//Read 0x18 : To check whether the PPM values are set accordingly

//Write 0x09, val: 0xFF : Set PPM Values
//Read 0x09 : To check whether the PPM values are set accordingly

// RMW to 0x0A val: [3:2] = 2'b00, CDR Reset
ReadBuffer[0] = 0x00;
Reg_Addr = 0x0A;
Status = EepromReadData2(Reg_Addr, ReadBuffer, 1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
MB_Sleep(1);

Reg_Mask = 0x0C;
Reg_Val = 0x0C;

clear_curr_val = ReadBuffer[0] & ~ Reg_Mask;
clear_new_val = Reg_Val & Reg_Mask;
combined = clear_new_val | clear_curr_val;

WriteBuffer[0] = 0x0A;
WriteBuffer[1] = combined;
BytesWritten = EepromWriteData(2);
MB_Sleep(1);

// RMW to 0x0A val: [3:2] = 2'b11, CDR Set
ReadBuffer[0] = 0x00;
Reg_Addr = 0x0A;
Status = EepromReadData2(Reg_Addr, ReadBuffer, 1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
MB_Sleep(1);

Reg_Mask = 0x0C;
Reg_Val = 0x00;

clear_curr_val = ReadBuffer[0] & ~ Reg_Mask;
clear_new_val = Reg_Val & Reg_Mask;
combined = clear_new_val | clear_curr_val;

WriteBuffer[0] = 0x0A;
WriteBuffer[1] = combined;
BytesWritten = EepromWriteData(2);
MB_Sleep(1);

//Read 0x02 : Read CDR Lock Status
while (1) {
ReadBuffer[0] = 0x00;
Reg_Addr = 0x02;
Status = EepromReadData2(Reg_Addr, ReadBuffer, 1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
MB_Sleep(1);
}

Hi,

I double checked this in the lab using a DS110DF410 evaluation board. I am able to acquire CDR lock to 1.0625Gbps input data with the following configuration.

0x09 = 0x04

0x18 = 0x30

0x60 = 0x80

0x61 = 0xAA

0x62 = 0x80

0x63 = 0xAA

0x64 = 0xFF

If the configuration above does not work for you there must be some other problem with either your system hardware or software.

Cordially,

Rodrigo Natal

Hi Natal,

We have done some Testing and below are our observations:

1. We tested with the Register configuration as shared by you and the CDR in the Retimer was not locking. This was our earlier result as well.
Hence we changed our design from 1.0625Gbps to 1.25 Gbps and done the required settings in the retimer to set it to standard Mode:
Reg_addr = 0x2f;
Data = 0x06;

This made the Retimer to Lock to the Incoming Data and we are receiving the data in the FPGA Receiver as well, without any Errors.
This confirms our design and the respective hardware is working.
Again when we reverted the Design to the Datarate of 1.0625, CDR is not locking.

We added the method of disabling the CDR Qualifiers as suggested by you in earlier and below are our observations:

Try disabling each of the CDR lock qualifiers, then check whether the retimer channel is able to lock to your 2.5Gbps signal
1. Disable Single Bit Transition (SBT) check -> Performed by setting 0x0C[3]=0
2. Disable PPM check -> performed by setting 0x2F[2]=0
3. Set the HEO/VEO lock thresholds to zero -> performed by setting 0x6A = 0x00
Try setting the retimer channel to CDR reference mode 0, and see whether the retimer channel is able to lock to your 2.5Gbps signal
4. This setting is performed by setting 0x36[5:4]=b00

Observations:

TC 1: No CDR Qualifiers disabled
Result: Reg 2[7:0] = 0x80/0x84/0xc4
i.e: Values are Toggling between 0x80, 0x84 & 0xc4

TC 2: All 3 CDR Qualifiers disabled
Result: Reg 2[7:0] = 0xd8/0x98 - CDR Locks, but the Signal from the output of the retimer is very distorted and cant capture properly on either CRO or FPGA Rx.

TC 3: 1st CDR Qualifiers disabled (SBT)
Result: Reg 2[7:0] = c0/80/40 - CDR wont Lock

TC 4: 2nd CDR Qualifiers disabled (PPM Check)
Result: Reg 2[7:0] = c4/84/80 - CDR wont Lock

TC 5: 3rd CDR Qualifiers disabled (HEO/VEO)
Result: Reg 2[7:0] = 02/04/06 - CDR wont Lock

TC 6: Retimer channel to CDR reference mode 0
Result: Reg 2[7:0] = c4/c0/44 - CDR wont Lock

Regards,

Ananthesh

Hi Natal,

One more input.

By Bypassing the CDR and enabling the RAW Data in the CDR, we are able to see the data at the output of the Retimer and able to receive the data without any errors in the FPGA.

Steps for Bypassing:

0x09[5] = 1'b1;

0x3f[7] = 1'b1;

0x1e[7:5] = 3'b000;

This gives me confidence that all the other environment is proper but the retimer configuration. 

Can you give your feedback on this.

Regards,

Ananthesha

What TI device was used for your latest round of tests, DS110DF410 or DS125DF410? The DS110DF410 will lock to 1.0625G while DS125DF410 will not.

Regards,

Rodrigo Natal

DS110DF410

Regards,

Ananthesh

Hi,

I don't yet have an explanation for the result you are observing. All of TI's retimer characterization results show the DS110DF410 is consistently able to acquire CDR lock to 1.0625Gbps. At this point I would recommend to set the channel to CDR bypass mode to run at 1GFC rate, as the retimer output jitter performance should still meet spec.

Regards,

Rodrigo Natal

At this point I would recommend to set the channel to CDR bypass mode to run at 1GFC rate, as the retimer output jitter performance should still meet spec.

Hi Sorry, i did not understand your last mail.

If you are asking to continue to use in CDR bypass mode itself: in which case right now our data path(copper cable) is shortened for testing purpose, the purpose of using retimer in the data path is to remove the attenuation and boost the signal performance over a lengthy 12 meters cable. If we use the retimer just to passthrough, equalization will not be taken care and the signal will be distorted.

Also do you mean GFC as Fibre Channel or is it datarate in Gsps itself.

Regards,

Ananthesh