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LMH0387: LMH0378 set up for SD-SDI communication

Part Number: LMH0387

Hi,

I'm using 2 LMH0387 devices as a receiver and transmitter and them work properly when I set them up for HD-SDI communication.

Now I want configure LMH0387s for SD-SDI but the transmitter does not work. The pin SD/HD is HIGH.

This is my question: Is the only configuration (pin SD/HD HIGH) required for the SD-SDI protocol? Is there a register to set?

thanks

Best regards

Bryan 

  • Hi Bryan,

    Is it the cable driver side or the equalizer side that is not working at SD? Can you please first make sure SD cable driver side works then we can check into the equalizer side.

    Regards,, Nasser

  • Hi Nasser,

    the equalizer side works properly because I receive all SD data from an external generator pattern.

    If I try to transmit SD data, it does not work. So the cable driver is the possible problem.

    I want to be sure that the hardware is set properly, so I can only concentrate on the FPGA software.

    The device works properly with HD-SDI signals in TX and RX.

    thanks

    Best Regards, Bryan

  • Hi Bryan,

    1). I believe you have already confirmed HD/3G cable driver works. This means TERMtx pin#45, Rref pin#36, TX_EN pin40, and other cable driver related pins are connected. Even if you did not have SD/HD pin set correctly your slew rate would have been incorrect.  I am assuming you see this issue on all devices ?

    2). Do you happen to have  access to a BERT? Is it possible if you can use this BERT and run at HD/3G which we know works. Once HD/3G works then on BERT switch only the data rate to 270M. I expect this to work since cable driver does not have intelligence - other than SD/HD to set slew rate properly - to determine whether this is SD or HD.  

    Regards,, Nasser

  • Hi Nasser,

    1) Yes, I have 2 LMHs and the issue is always present.

    2) I have not acess to a BERT.

    I send you the connection schematic. I already change C27 with a 1uF capacitor.

    TX_EN = '1'

    SD/HD = '1'

    register x"00" <- value x"10" (force equalizer sleep).

    I used an Intel'IP on my FPGA that should generate SD_SDI signal. It uses a 148.5 MHz clock signal as reference  and 1 pixel (Y-Cb/Cr) last 11 clock cycles (13.5 * 11 = 148.5 MHz). It  uses a data_valid signal at 27 MHz to sample Y and Cb, Cr.

    I wanted to be sure that is not an hardware problem and that I set properly LMH device as SDI-SD transmitter.

    Thanks

    Bryan

  • Hi Bryan,

    Given HD/3G cable driver works, i don't see a reason why SD should not not work. Your hardware looks fine to me. I compared regular evaluation board schematic.

    Regards,, Nasser

  • Hi Nasser,

    thank you for the support.

    Regards,

    Bryan