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Original question:

DP83867IR: DP83867 1000-BASETX Configuration

DP83867IR: software reset issue

sarath sai
Intellectual 325 points
Part Number: DP83867IR

Hello,

i'm using DP83867IR in RGMII mode  based on the link  phy is detecting the speed but from the Emac RX_CLK  is different from that of the  evolution board. i'm using analog devices based SHARC development baord(SC589-ezkit)  based on that i have designed the custom hardware i can able to check the rx clk on Analog devices board rx clock for gigabit operation it  is 125MHZ with 700mVp-p but with my custom hardware amplitude has been reduced to 250mVp-p but still im getting 125MHz wht might be the issue please check the attached schematics Please as per recommendations i have removed 3.3V  from the magnetics but still i have not updated schematics assume that magnetics is unconnected to any supply.

  • 0
    Intellectual 325 points

    because of this software reset is not happening ?? my code is getting hanged at the software reset adn phy is getting diabled

  • 0 in reply to sarath sai
    TI__Genius 11725 points

    Hi Sarath,

    When probing for these values, are you probing near pin 32 of PHY or near the MAC? How long is trace length between PHY and MAC? How is RX_CLK being used to determine software reset? Software reset happens through MDIO/MDC pins so it's not clear how RX_CLK affects this. Additionally, ensure that the center taps of the magnetics are not shorted together. Refer to Figure 30 in the datasheet.

    Thank you,

    Nikhil 

  • 0 in reply to Nikhil Menon
    Intellectual 325 points

    Hello NIkihil,

    we sorted out the software reset issue from the mac there was problem with RX clock.From the MAC datasheet we understood that, The reset operation is completed only when all the resets in all the active clock domains are de-asserted.Therefore, it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. 

    In PHY pin no 32(RX_CLK), and  33(RX_D0) when we establish the link we are observing same 125MHz for 1000MBPS  and 25MHz for 10/100 respectively   for the DATA PIN RX_D0 and RX_CLK  also we checked the short between two pins but it was open and for your information the trace length is around 850mils but in the evolution board of analog devices it is around 4100mils i assume that trace length is not the issue and i told you earlier that i have isolated the magnetics from 3.3V so center taps  are not shorted together they are independently connected with 0.1uF to gnd. Still my code is getting hanged at the interrupt  after coming out from the software reset what might be the problem  ??

    Regards

    Sarath

     

  • 0 in reply to sarath sai
    Intellectual 325 points

    Hello Nikhil

    Since from morning we have debugged PHY still we  are not getting how at the data pin RX_DO we are getting the 125MHZ clock there is no short present between these two pins RX_D0 and Rx_ClK because of this phy is getting hanged at the interrupt it is not coming  out of the interrupt.

    Regrads

    sarath 

  • 0 in reply to sarath sai
    TI__Genius 11725 points

    Hi Sarath,

    Is the RX_CLK amplitude problem resolved? Is the 125 MHz clock on the RX_D0 a new issue? When your software is getting hanged at interrupt, is this the PHY interrupt? Can you access the registers of the PHY? If so, can you read registers 2 and 3? 

  • 0 in reply to Nikhil Menon
    Intellectual 325 points

    Hi Nikhil,

    Our issue has been resolved. the PHY started working in Gigabit and auto negotiation itself we were generating the clock for PHY through our controller and amplitude levels are not good enough for the phy so we kept  independent clock(oscillator) for the phy after that it started working continuously 

    Regards

    Sarath