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SN65DSI86: ASSR control

ajayt
Genius 9555 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Is it possible to disable ASSR in SN65DSI by writing b00 to bits 1:0 in register 0x5A?  On page 48 in datasheet it is stated

“ASSR_CONTROL.This field controls the scrambler seed used. Standard DP scrambler seed

value is 0xFFFF. The ASSR seed value is 0xFFFF. This field is R/W if TEST2 pin is sampled

high on rising edge of EN and bit 0 of offset 0x16 in Page 7 is set. Otherwise this field is readonly.

00 = Standard DP Scrambler Seed.

01 = Alternative Scrambler Seed Reset (Default).

10 = Reserved.

11 = Reserved”

We appreciate answer on this question very soon since we are now doing changes for the second spin of our board, and we haven’t been able to get eDP working. On the first spin we have tied TESTS2 (B5) directly to gnd. On the second spin we will make it possible to connect it to high level. The question is will this solve our problem, or do we need another solution?

 

Is it then possible to use a panel that doesn’t support ASSR, when Standard DP Scrambler Seed is selected?

  • 0
    TI__Guru**** 179426 points

    Please make sure TEST2 pin is high, and then

    ======ASSR RW control ====== 
    <i2c_write addr=0x2D count=1 radix=16> FF 7 </i2c_write>/> 
    <i2c_write addr=0x2D count=1 radix=16> 16 1 </i2c_write>/> 
    <i2c_write addr=0x2D count=1 radix=16> FF 0 </i2c_write>/>

    I would make sure the internally generated color bar works first with the eDP panel.

    Thanks

    David