DS90UB936-Q1: Serializer and DeSerializer Data Rate configuration

Hi Ganesan,

Are you asking about the FPD link rate between the Ser and Des? Typically that's not what you limit; rather, you want to limit the output of the Deserializer CSI Tx port or in other words, the input into the SoC. I'd recommend changing the CSI Tx speed per lane, which is configurable via register 0x1F[1:0] on the DS90UB936-Q1. You can set this to 200Mbps, 400Mbps or 1.6Gbps per lane. You would send in let's say less than or equal to 400Mbps/lane from the imager -> Serializer -> Deserializer ->Output 400Mbps/lane. As long as the output from the imager is less than or equal to what the CSI TX speed is of the Deserializer, you are good.

FYI, the FPD link rate is fixed at 4Gbps or 2Gbps.

Regards,
Mandeep Singh

I don't understand how the FPD link rate is fixed at 4Gbps or 2Gbps. The datasheet of DS90UB935 and DS90UB936 says the data rate is 3Gbps but for CSI-2, it 2.528Gbps. I assume this is fixed speed for these devices. If you look at the drawing attached, maybe you can comment if the data rate is correct. I like no more 1000Mbps due to EMC issues if can be done.