DS90UB953-Q1: Can not Transmit Pattern from 953 to 960

Hi Thomas,

Glad to hear the pattern generator on the 960 is working well.  Before we hop over to the pattern generator on the 953 and test it over the link, lets first test the link.

Please let me know what the results are from running this script: P960_953_BIST_AllPorts.py

It is found in: Analog LaunchPAD v1.57.0010\PreDefScripts\DS90UB960

Please copy and paste the results from the terminal after the script is run.  It utilizes the BIST with descriptive output.  If everything checks out, our next step will be to try the pattern generator.

For that, a similiar script would be: 953to954_patgen_YUV_1920x1080p-4Lanes-Working.py

Now, this script is written for the 954 and may require a little modification when using the 960, but is a good example to follow for configuring the 953 patgen remotely over the link. 

It is found in: Analog LaunchPAD v1.57.0010\PreDefScripts\DS90UB954

Sincerely,
Bryan Kahler

Hi Bryan, thanks for your Help.

I have excecute the script, and the Output was:

>*** Running P960_953_BIST_AllPorts.py ***
  RX0
Devices Reset
('960 Device ID (0x00):', '0x0')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x0')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################
  RX1
Devices Reset
('960 Device ID (0x00):', '0x0')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x0')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################
  RX2
Devices Reset
('960 Device ID (0x00):', '0x0')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x0')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################
  RX3
Devices Reset
('960 Device ID (0x00):', '0x0')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x0')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################

Hi Thomas,

Thank you for the output from the script.  This script assumes that you're communicating with the 960 via local I2C and that the I2C address of the 960 is 0x7A.  If the address of the 960 is not 0x7A, please modify the script to use the I2C address that is being used for the 960 in your set up.

Sincerely,

Bryan Kahler

Oh yes, the Address is 0x70

The new Output from the script is:

  RX0
Devices Reset
('960 Device ID (0x00):', '0x70')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x3')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x8')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################
  RX1
Devices Reset
('960 Device ID (0x00):', '0x0')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x0')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################
  RX2
Devices Reset
('960 Device ID (0x00):', '0x0')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x0')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################
  RX3
Devices Reset
('960 Device ID (0x00):', '0x0')
('953 Device ID (0x00):', '0x0')
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bit [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Read BCC Error Status (0x79):', '0x0')
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 before BIST.', '0x0')
------------------------------------------------------------------
('Read BIST CTL register (0xB3) Before BIST ENABlED', '0x0')
Should read 0x00 or 0x08

('Read BIST CTL (0xB3) register After BIST ENABLED', '0x0')
Should read 0x01
------------------------------------------------------------------
('Read BIST Lock Status Change of 960 RIGHT AFTER BIST enabled (0x4D):', '0x0')
Read to clear BIST enable Lock Status Change.
('Read Post-BIST Lock Status Change of 960 RIGHT BEFORE BIST disabled (0x4D):', '0x0')
bits [1:0] should be high i.e. 0x3, If lock status changed during BIST, bit [4] will be high
------------------------------------------------------------------
('Reciever Lock Status (0x4D):', '0x0')
Bits [1:0] should be high. i.e. 0x13
------------------------------------------------------------------
('Pre-Error Link Status of 953 (0x52):', '0x0')
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
------------------------------------------------------------------
('BIST CRC Error count (0x54) on 953 after BIST.', '0x0')
('Parity Error count MSB (0x56) on 960.', '0x0')
('Parity Error count LSB (0x55) on 960.', '0x0')
------------------------------------------------------------------
#################################################################

Hi Thomas,

There is no response from the 953.

Can you conifrm:

1) Power to the 953

2) Check 960 is in CSI-2 mode

3) Check 960 for lock

4) I2C Passthrough enabled on 960

At this point, you should be able to rerun the script above and get a response from the 953, assuming all of the above are proper.

Please let me know if/where issues crop up in these steps.

Sincerely,
Bryan Kahler

Hi Thomas,

Thank you for the update - glad to hear the test pattern generation was successful.

Please let us know if there are any other issues.

Sincerely,

Bryan Kahler

Hi Bryan,

at present we are dealing with BIST of FPDL3 with 960 - 953 as well.

I read there is a script for testing this (P960_953_BIST_AllPorts.py), but at my APL on PC there is no PreDefSripts directory at all.

May be it is to old (installed in 2018) ...

Is that script available additionally?

Sincerely,

Torsten Kilias  

Hi Torsten,

Please install the latest version of ALP and also install the ALP-Profile-Update.

Both may be found here: http://www.ti.com/tool/ALP

If you install in the non-default path, on some systems the profile update may nest folders unexpectedly. 

Sincerely,
Bryan Kahler

Hi Bryan,

thanks for your hints.

Despite of "never change a running system" I already had installed v1.57.0010 - there are significant differences after a re-installing.

Unfortunately the GUI stability is not getting better, from time to time it restarts.

Now I am adapting the 960-953 BIST sript to our conditions.

Concerning "Consult Register 0x79 on the SER for more information" - there is no explanation of reg. 0x79 in 953 data sheet?

Where to find more information?

Sincerely

Torsten Kilias 

Hi Bryan,

meanwhile we adapted the 960_953_BIST script to our conditions.

We got following result:

There is still the question concerning reg. 0x79 of 953.

Then there is always a BC error in communication and what is the explanation of the errors in last section?

Sincerely

Torsten 

Hi Bryan,

there are still unanswered questions regarding Register 0x79. In the datasheet it is described as "reserved".

This application report: http://www.ti.com/lit/an/snla267a/snla267a.pdf gives some more information:

Do we have any further documentation on the functionality of this register?

Sincerely,

David

Hi Torsten,

Thank you for running the script.

The errors may indicate intermittent lock conditions.

Please poll register 0x4D every second for a few minutes to test the change of state of the register.   Looking to see if we catch frequent state changes and/or unlocked state.

If frequent state changes are seen, please describe your setup and connections between more devices in detail.  For example, are these custom boards or evms, what cables are being used, etc...

There is also a MAP tool that may be used to investigate the link conditions of the forward channel.

Sincerely,

Bryan Kahler

Hi Bryan,

thanks for your hints.

I added polling of reg. 0x4D to the script. Even increasing to 200 measurements (one per second) did not yield a single Lock Status Change.

The other results are relatively reliable and stable. 

The information concerning reg. 0x79 of SER is still missing.

Our system is based on a self designed ECU (TDA based) with 960 DES and a self designed camera (with 953 SER), working in CSI-2 mode.

Data are transmitted via TP on a DACAR 535. For BIST DES and SER are powered up with default register settings. 

PS: Is it possible to start a BIST in DVP mode too? 

Regards

Torsten 

Hi Torsten,

It appears there was a lock drop during BIST.  Please run the margin analysis and share the results.  Also, is a POC network being used?  If so, please share your schematic including the POC network.

Sincerely,
Bryan Kahler

Hi Bryan,

attached you will find passed margin analysis. It seems to be reliable.

We do not use POC. SER is connected via TP, i.e. there is a separate power supply for SER.

Regards,

Torsten

Hi Torsten,

Please send the schematic of the ser/des boards for review.

Sincerely,

Bryan Kahler