TCAN4550: Configure NBTP and DBTP

Hello Steve,

If I decode your NBTP register value correctly you have the following settings:

NTSEG2 = 0x03 (or 4 time quanta)

NTSEG1 = 0x0E (or 15 time quanta)

NBRP = 0x01 (Pre-scaler of 2)

If you are using a 20Mhz clock, and there is a pre-scaler of 2, you will have 10 time quanta available for a 1Mbps bit rate and since you are using 20 time quanta for your time segments, you are properly configured for a 500kbps bit period with an 80% sample point. I might suggest not using a pre-scaler of 2, and have more time quanta available for tune the sample point.

I will walk through a breakdown and build up my suggested values to try.  Section 3.1 of the Software User's Guide also discusses this and is a good resource if you have not read it yet.

A 1Mbps bit rate would require 20 time quanta (tq) in no pre-scaler was used.  If a pre-scaler of 2 was used, then only 10 tq are used for a 1Mbps. The actual bit rate is then created by defining how many tq are used for the various segments.  Using more tq will create a slower bit rate, and using fewer tq will create a faster bit rate. 

The bit period is created by defining the number of time quanta for three segments and taking the sum.  The sync segment which is always 1tq, followed by the NTSEG1 or the Nominal time segment before the sample point), and lastly, the NTSEG2 or the nominal time segment after the sample point.

Adding up your NTSEG1 + NTSEG2 + 1 tq (for sync) = 20 tq.  If you were wanting an arbitration bit rate of 500kbps, this would be a correct configuration.  I will also note that the NSJW is typically set equal to NTSEG2, and that is set correctly for your configuration.

If you want a 500kbps Arbitration rate without using a pre-scaler, you will need to define the segments based on a total of 40 tq since 500kbps is half of the 1Mbps rate when a pre-scaler of 0 (interpreted as 1) is used.

I would suggest the following segment values to try for 500kbps with a sample point at 80% of the bit period. 

NTSEG2 = 7 (interpreted as 8, always one less than the raw value because the TCAN4550 will add 1) = 0x07

NTSEG1 = 30 (interpreted as 31, always one less than the raw value because the TCAN4550 will add 1) = 0x1E

NBRP = 0 (interpreted as 1, always one less than the raw value because the TCAN4550 will add 1) = 0x00

NSJW = 7 (interpreted as 8, then remember to shift by one to add bit 8 of NBRP to the beginning of this byte ) = 0x0E

This would create a final NBTP register value of 0x0E001E07 for a 500kbps bit rate.

The process is the same for the Data Bit rate configuration but the DBTP register bits are configured a little differently than the NBTP. For 2Mbps I would recommend the following DBTP settings with a sample point of 80% of the bit period.  There will be 10 tq per bit for a 20Mhz clock and a pre-scaler of 1.

DTSEG2 = 1 (interpreted as 2, always one less than the raw value because the TCAN4550 will add 1) = 0x01

DTSEG1 = 6 (interpreted as 7, always one less than the raw value because the TCAN4550 will add 1) = 0x06

DBRP = 0 (interpreted as 1, always one less than the raw value because the TCAN4550 will add 1) = 0x00

DSJW = 1 (interpreted as 2,always one less than the raw value because the TCAN4550 will add 1) = 0x01

TDC = 1 (Transmitter Delay Compensation enabled)

This would create a final DBTP register value of 0x00800611 for a 2Mbps bit rate.

You will also need to set the TDCO (Transmitter Delay Compensation Offset) register to match the "interpreted" value of DTSEG1 value.  The TDCO does not interpret the value as 1 greater than the set value, so TDCO = DTSEG1 + 1.  This would mean you would want to set the TDCO to 7 =0x07.

This would create a final TDCR register (0x1048) of 0x00000700 for a DBTP register value of 0x00800611.

I believe these settings should work, but I also hope I provided enough information for you to be able to adjust them for different bit rates.  There is no one answer, and you can adjust the sample point and time quanta to optimize the performance of the network. However you could try moving the sample point on the arbitration bit closer to the center point if you are having arbitration issues.  You are set at 80% now, and you could try moving it to between 70% and 75%

I would also recommend you try a NBTP value of 0x14001B0A (1 + 28 + 11 = 40 tq), with a sample point of 72.5%.

You could also try bumping the data bit sample point down to about 70% as well if you find problems with data bit sampling.  You could try:

DBTP = 0x00800522

TDCR = 0x00000600

Regards,

Jonathan

Hi Steve,

I realized I made a simple oversight in my original post by not adding the +1 interpretation to the pre-scaler register.  I have edited my original post to correct the errors and I added a couple other suggested values to try.  I apologize for any confusion that may have resulted from my original post last night.

Please let me know if you have any further difficulties.

Regards,

Jonathan

Hi Jonathon,

Thank you for writing the helpful post.

I did catch the error on the bit time calculation.  I am currently running NBTP = 0x0E001E07

To get a 2MHz FD rate I found DBTP = 0x00810111 (5 Quanta?)

I Set TDCR = 0x00000200 as suggested.

I have terminated the network with 120 ohms.

With classical CAN the data read by my Peak sniffer is solid - no errors.  With CAN FD   I am getting intermittent stuff and other timing errors.

In my application we will be using both classical CAN and CAN FD. This will not be concurrently.  We will poke our device under test and determine its mode.

The application is fairly simple and we will not be using much of the capability of this device.  It is very impressive and comprehensive.

Thanks again for the help.  If you have any more thoughts I'd love to hear them.

Best regards,

Steve

Hi Steve,

I'm glad to hear that you have the classical CAN data working without errors. 

For the faster CANFD bit rates, the bus wiring topology and network can create some inductive ringing following a bit transition that need to decay before sampling the bit.  This is why we will typically see a sample points around the 80% point in the bit period.  You could try to shift tq from the DTSEG2 to the DTSEG1 values to delay this sample point.  If you need a finer resolution, you can remove the pre-scaler and give yourself more tq to work with. 

You mentioned that you terminated with 120 ohms.  Is this only terminated in one location, or is there another 120 ohms at the other end of the bus?  The bus is typically terminated with a 120 ohm resistor at the two ends of a bus, or 60 ohms in the center of a "Star" topology.  If you only have a single 120 ohm termination, you could make that 60 ohms, or add another 120 ohms in parallel across the bus to give the proper loading the transceiver was designed to drive.

Have you used a scope to observe the CAN waveforms?  Observing any noticeable ringing could help determine how far the sample point needs to be adjusted or point to other physical layer issues that may be present. 

Regards,

Jonathan

Hi Jonathon,

We do have termination on each end, the signal path is very short (5cm) and the ringing is minimal.  We'll clean up the test bench and see if it improves.

I have now moved to receiving a message with the setups we have established.

I am going to have dedicated RX buffers (just 1), and a single standard filter.  The FIFO's have been disabled.

What I am seeing is a message is received without regard to the filter matching the message.  When I look at the RX buffer it is all 0's ... No ID, FDF, BRS or buffer offset.

The NDAT1 bit 0 is set to indicate something arrived.

Here is my setup:

// In Restricted set up ....

   //  SID Filter
       tcam_words[0].cmd32 = 0x00010000;      // at 0x8000  1 filters
       AHB_Write_32(REG_MCAN_SIDFC);      

       //  XID Filter
       tcam_words[0].cmd32 = 0x00010008;     // at 0x8008
       AHB_Write_32(REG_MCAN_XIDFC);
       
       //  FIFO 0
       tcam_words[0].cmd32 = 0x00000000;    // No FIFO 0
       AHB_Write_32(REG_MCAN_RXF0C);   
 
       //  FIFO 1
       tcam_words[0].cmd32 = 0x00000000;    // No FIFO 1       
       AHB_Write_32(REG_MCAN_RXF1C);   
   
        //  RX Buffer Control
       tcam_words[0].cmd32 = 0x00000100;    // RX Buffer at 8100
       AHB_Write_32(REG_MCAN_RXBC);
       
       //  Element Size control
       tcam_words[0].cmd32 = 0x00000000;    // 8 byte data blocks       
       AHB_Write_32(REG_MCAN_RXESC);
      

// End of set up

// Filter:

       tcam_words[0].cmd32 = 0xBEDD0000;    // Filter 0x6DD reply,  SFEC 111
       AHB_Write_32(0x8000);
       
       tcam_words[0].cmd32 = 0x00000000;    // Clear RX buffer status bits
       AHB_Write_32(REG_MCAN_NDAT1);
       AHB_Write_32(REG_MCAN_NDAT2);

// Test for data

AHB_Read_32(REG_MCAN_NDAT1,2);         // Read both receive status registers

// Read Data

           AHB_Read_32(0x8100,4);

This seems straightforward.

I must have 1 bit or parameter set wrong.

Let me know if you see something.

Thanks, again!

Have a great weekend.

Steve

Hi Jonathon,

Did you see my last post about receiving CAN messages.

This is the last piece I need help with to get my project finished up.

Thanks,

Steve

Hi Steve,

Yes, I saw your last post and I am currently looking into it.  I apologize for not being able to get you a more meaningful response sooner and I will follow up with you soon.

Regards,

Jonathan

Hi Steve,

Great!  Thanks for letting me know.  I was wondering how that was configured and looking for any other relevant bits that might not have been set properly that weren't listed in your prior post.  I am glad you got it working and feel free to ask as many questions as you would like.

Have a good evening!

Regards,

Jonathan