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DS90UB953A-Q1: CLK_OUT jitter characteristics

6056811
Prodigy 50 points
Part Number: DS90UB953A-Q1
Other Parts Discussed in Thread: CDCI6214, DS90UB953-Q1

Hi,

in our application, we are using a 953 together with a 954.

The 953 is configured in Synchronous mode, therefore it recovers the clock from the deserializer (954).

The 954 has a PLL (CDCI6214) as clock source. This clock source provides a 25MHz clock reference.

On the serializer side, we would like to have a 50MHz clock to source an FPGA.

As the FPGA has a relative high requirement of maximum clock jitter, I would need to know if you have measured the jitter in the whole temperature range of the device, with similar configuration to the one mentioned above.

Any further information on CLK_OUT functionality is welcome.

Thanks in advanced.

Santiago 

  • 0
    TI__Guru** 103215 points

    Hello Santiago,

    Thanks for reaching out. Could you share the jitter requirement for this? Also are you using the SCC function on the REFCLK source?

    Best Regards,

    Casey

  • 0 in reply to Casey McCrea
    Prodigy 50 points

    Hello Casey,

    Thanks for your reply. 

    The jitter requirement is: Period Jitter < 500 ps p-p

    We are not using SCC function on any clock source.

    It may be important also to point out that the system runs in a temperature environment from -40°C to 100°C

    Best regards,

    Santiago 

  • 0 in reply to 6056811
    TI__Expert 3390 points

    Hi Santiago,

    The main factor for clk_out jitter is the N/M divider ratio, if this is not an integer, it will contribute to some jitter on the link, typically in the 1-5ns range. However, for a 50MHz clock, you can select an M = 1 and N = 20 and therefore the jitter should be low. Configuring the CLK_out is documented in the DS90UB953-Q1 datasheet section 7.4.1.5. To get the 50MHz clock out, you can set Register 0x06 = 0x41 and 0x07 = 0x14 in the DS90UB953-Q1 registers. Because there's multiple factors involved in a system level testing, I suggest that your team measures the CLK_Out jitter and ensures it's meeting your spec.

    Regards,
    Mandeep Singh

  • 0 in reply to Mandeep S
    Prodigy 50 points

    Hi Mandeep,

    thanks for your reply.

    We will measure it by ourselves then.

    Regards,

    Santiago Tonietti