DP83867IR: How to operate Loopback mode of DP83867IRRGZ

Feng bin Su

Expert 8920 points

Part Number: DP83867IR

Hi team,

My customer have some issue on Phy DP 83867, currently the result is.

The MDIO interface is working and I can read the Phy register by MDIO interface.
But the data bus between MAC and PHY is un-working.

Their questions is:

How to make sure the BUS is working at LOOP back mode?
How to control MAC to send raw data and compare the return value?
Did you have test example code?

Thanks.

over 6 years ago

0 Vibhu Vanjari over 5 years ago

TI__Genius 11900 points

Hello Feng,

The "8.4.4 Loopback Mode" section of the datasheet explains the different loopback modes within the PHY, including what registers need to be configured to enable the different loopback modes.
You will have to refer to the MAC datasheet for this one
What test code are you looking for? To set the PHY to loopback you need to write the required values to through the SMI interface (MDIO/MDC).

Thanks,

Vibhu

0 Feng bin Su over 5 years ago in reply to Vibhu Vanjari

TI__Expert 8920 points

Hi Vibhu,

Thank for your reply.

Currency the PHY DP83867 can working right now, I think it is came from by FPGA clock setting and pin assignment issue.

But customer have another question.

How to define the RX/TX internal delay value in Linux device-tree?

Example:

Ethernet-phy@0 {
	reg = <0>;
	ti,rx-internal-delay = <??? DP83867_RGMIIDCTL_2_25_NS>;
	ti,tx-internal-delay = <??? DP83867_RGMIIDCTL_2_75_NS>;
	ti,fifo-depth = <??? DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};

0 Vibhu Vanjari over 5 years ago in reply to Feng bin Su

TI__Genius 11900 points

Hello Feng,

I would suggest experimenting with the RGMII TX and RX delays. The skew required depends on how your board is set up and how long the traces are. You shouldn't have to change the fifo-depth is there a reason you are using this control?

Thanks,

Vibhu

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DP83867IR: How to operate Loopback mode of DP83867IRRGZ