DP83867CR: Bootstrap recognition varies depending on the rising slope of reset

Hi,

I have additional information about this issue.

I have a DP83867ERGZ EVM and confirmed this phenomenon.

I attached resistor R35=10K, R36=2.49K and removed C6 on the EVM. We can see that RX_D2 pin goes up the voltage at  releasing reset.

So, please reply my questions.

Best regards,
Kenshow

Hello Kenshow,

What are the values of your resistors on your board? You will need to account for the pull-up resistors or any driving voltages on your MAC pin connected as well.

On the EVM after you release from reset, do you read register settings to confirm that the pins have set the PHY to the right state, can you please check this?

Why was C6 removed? The RESET input must be held low for a minimum of 1 us.

Thanks,

Vibhu

Hi

I am sorry for the late reply.

I noticed that the strap voltage may have exceeded the maximum in custom board. So, we are investigating, now.

I removed C6 because I wanted to observe the case where the reset rises early. Because there is a switch, it is not necessary to add on C6 to hold Low for at least 1 us.

Thanks,
Kenshow

Hi Vibhu,

The strap voltage on the custom board was adjusted to be within the target voltage, but it did not improve.

My questions are:

1) Why is the RXD2 signal affected by the Reset signal? (Strap reads at different voltages) What are the factors?

2) Why does the voltage rise slowly even for signals that are connected only to DP83867, such as LED2? (This can also be confirmed with TI EVM.) What are the factors?

Regards,
Kenshow

Hi Vibhu,

 Can you reply about my questions?

 Or, in case of behavior like RX_D2, please answer whether the countermeasure by adding a slope to the reset is correct.

Regards,
Kenshow

Hello Kenshow,

Please see my statement above "You will need to account for the pull-up resistors or any driving voltages on your MAC pin connected as well." Please confirm that you are using the EVM without any connections to the MAC with the recommended resistor values according to the datasheet. I suspect there is an issue with the MAC internal pull-up resistor.

As long as the voltage of strap configurations is met and all "7.7 Reset Timing" requirements as well as power sequencing requirements if using 3-supply mode (Figure 35), I wouldn't expect issues. I would still strongly recommend you to try bootstrapping the PHY without the MAC to narrow down the problem first.

Thanks,

Vibhu

Hi Vibhu,

 The reset and power-up timing are OK on the custom board.

 I checked DP83867IRPAP-EVM using waveform generator for reset signal  and got the wave of reset rising and RX_D2 as follows:

Blue:RESET, Yellow:RX_D2. Reset sloop is 5nsec. 

RX_D2 has an amplitude of 100mV or more at reset, which seems to affect the strap voltage.

Is there any problems with this waveform?

Does a capacitor need to be connected to RESET to solve this problem?

Regards,
Kenshow

Hello Kenshow,

Please try reconnecting C6 this should smooth out the ringing. Let me know if that doesn't work.

Thanks,

Vibhu

Hi Vibhu,

I know that ringing is smoothed by connecting a capacitor to RESET and will be solved this issue.

Please look at waveform of wave.pdf at my first posted.

This suggests that even if the power supply and reset sequence are designed as specified in the data sheet, the reset voltage from the logic may affect the strap voltage depending on the I/O on the MAC side. Is it correct to slow the rise of RESET to solve this?

Regards,
Kenshow

Hello Kenshow,

The recommended solution is to set the internal pull resistors of the MAC to a known state (known internal pull-up or pull-down, keeping in mind tolerances) or hi-Z when releasing the RESET of the PHY. The bootstrap resistors can then be selected to meet the voltage requirements shown in the datasheet.

Slowing down the RESET has not been validated so I cannot confirm this solution.

Thanks,

Vibhu

Hi Vibhu,

Thank you very much for your support.

When setting Mode2, I point out that even if the strap voltage is adjusted with the internal and external PU/PD, the voltage of 100mV or more will rise, so the voltage of Mode2 cannot be satisfied. 

If slowing up the RESET will not be verified, could you explain the mechanism that affects the voltage level inside the PHY device due to reset release?

Regards,
Kenshow

Hello Kenshow,

Is it possible to switch the MAC pins to Hi-Z during PHY reset? After you use the slowing RESET method, when you read 0x006E and 0x006F do you see the correct strap settings selected there?

The PHY pins voltage during reset is gauged and this determines what mode the PHY is bootstrapped into. During reset only the pin's internal pull-down resistor and any external to PHY devices will effect the behavior of the mode it latches too.

Thanks,

Vibhu

Hi Vibhu,

I appreciate your help.

> Is it possible to switch the MAC pins to Hi-Z during PHY reset?
MAC is input I/O with PU. it cannot remove PU. We cannot remove  MAC device.

> After you use the slowing RESET method, when you read 0x006E and 0x006F do you see the correct strap settings selected there?

We cannot see the register, but recognize PHY adress is changed.
The Slowing RESET is OK.

> The PHY pins voltage during reset is gauged and this determines what mode the PHY is bootstrapped into.
> During reset only the pin's internal pull-down resistor and any external to PHY devices will effect the behavior of the mode it latches too.

Why does the strap pin increase voltage when reset is released?
We are looking at the problem that the voltage at the strap pin goes up when reset is released. This was confirmed by EVM. I would like to know why the strap pin voltage rises when reset is released.

Regards,
Kenshow

Hello Kenshow,

Reading the registers would be the best way to confirm that the bootstrap settings worked. If you are using the EVM why can't you access the registers?

I will look into the strap pin voltages and get back to you.

Thanks,

Vibhu

Hi Vibhu,

 I cannot access registers of EVM because I don't have MDIO tool for VDDIO=1.8V. 

EVM with a slope for RESET release has the following waveform.

RX_D0 on EVM has a similar waveform. In this case, the register value is considered normal from the result of the custom board.

From the waveform in EVM, We suspect that Rx_D2 of the custom board may be affected by the MAC side or layout, too.

Then, I have a question:

Regards,
Kenshow

Hello Kenshow,

Please contact your FAE for a MSP launchpad to read the register voltages. After reading the registers you will be able to determine if the PHY has entered the right mode and the strap settings were accurate.

To answer your question this rise in voltage that you see is not a specification of the PHY device. After reset the voltages are sampled before the PHY goes into a certain mode.

Thanks,

Vibhu

Hi Vibhu,

Thank you for your reply.

I agree that the voltage is sampled after the reset is released and before the PHY enters a specific mode. 

Apart from this problem, I would like to know if the waveform in my previous post is normal as DP83867. If your answer is "No", please check your EVM.

Regards,
Kenshow