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DS90UB953-Q1: DS90UB960-Q1 + DS90UB953-Q1 + sony imx390

Amy Luo
Expert 6895 points
Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: DS90UB960-Q1, TIDA-020002, , ALP

Hi TI team,

My customer has the following problems, which are described in Chinese. I am not familiar with SerDes products. I translate the questions from Chinese to English. If you are confused, please point out.

Currently, ti960 / ti953 / and imx390 can be accessed through I2C (the correct signal of I2C at the sensor end can be measured)

Hardware:

POC filter; refer to ds90ub960-q1 figure 40. Typical POC network for a "4G" FPD link III

REFCLK: 25Mhz ( 100ppm)

Mode : Strap Configuration Mode Select; No.4 of Table2. /CSI-2 Mode

Set up:

Roughly refer to design guide: tida-020002

FPD-Link III I2C Initialization

But csi0 output MIPI signal is intermittent. There is no way to output a complete image.

It is found that the setting may be discontinuous

Register 0x33 with 0x01: without Enable CSI-2 continuous clock mode.

But it was found in the documents

Ds90ub953-q1 page 17, csi-2 is divided into short and long packet (including VC / Data ID...) how to confirm or set the output short packet?

In addition, ds90ub953-q1 modifies Reg 0x06/ 07 CSI0 to output MIPI, which seems to have an impact, but how to adjust it correctly??

Best Regards,
Amy Luo

  • 0
    TI__Prodigy 620 points

    Hi Amy,

    Firstly regarding to your questions, please refer to below that:

    Ds90ub953-q1 page 17, csi-2 is divided into short and long packet (including VC / Data ID...) how to confirm or set the output short packet?

    [CH] The long/short packet just be defined by MIPI protocol, so you don't need to set up it.

    In addition, ds90ub953-q1 modifies Reg 0x06/ 07 CSI0 to output MIPI, which seems to have an impact, but how to adjust it correctly??

    [CH] If this seems have an impact, maybe it's the issue cause, and for correct configuration:

    1st you need to know what's the PCLK the image sensor need.(refer to sensor datasheet)

    2nd you need to configure 953's CLKOUT as value above according to below equation.(also more detail you can refer to DS90UB953 datasheet's section -7.4.1.5)

    BTW, as this is a system design, so except refer to TIDA-02002, I also suggest you can share below AN to your customer, it include a detail design flow and other guideline/design tips, and it should be helpful here.

    Thanks & BRs,

    Cheney

  • 0 in reply to Cheney Hu
    TI__Expert 6895 points

    Hi Cheney,

    Thank you for your answer.

    In your reply above, I didn't find AN that can be shared with customer. Could you attach it again.

    The customer added the following question, could you give your answer.

    DS90UB960-Q1 sets pattern generation

    # Set CSI Timing parameters for 400Mbps operation (both ports)
    board.Ind_Acc_Write(0x0, 0x40, [0x83, 0x8D, 0x87, 0x87, 0x83, 0x86, 0x84, 0x86, 0x84], 9)
    board.Ind_Acc_Write(0x0, 0x60, [0x83, 0x8D, 0x87, 0x87, 0x83, 0x86, 0x84, 0x86, 0x84], 9)

    How can the above settings be realized with I2C on microprocessor?

    # 1920*1080 @ 30 fps
    # 4 x lane 400Mbps/lane
    # Data Type: YUV422 10-bit

    # Data
    #
    # ` pixles
    # Vactive:1080 lines
    # Vtotal:1125 lines
    # Vfront:10 lines
    # Vback:33 lines
    # Pixel size: 20 bits (Mipi CSI-2, Table 15 )
    # Block size: 5 bytes (Mipi CSI-2, Table 15 )
    # Frame rate: 30 fps
    # Number of bars: 8
    #
    # Reset
    board.WriteReg(0x01, 0x01)
    # Set CSI_TX_SPEED to select 400Mbps
    board.WriteReg(0x1F, 0x03)
    #
    # Set CSI Timing parameters for 400Mbps operation (both ports)
    board.Ind_Acc_Write(0x0, 0x40, [0x83, 0x8D, 0x87, 0x87, 0x83, 0x86, 0x84, 0x86, 0x84], 9)
    board.Ind_Acc_Write(0x0, 0x60, [0x83, 0x8D, 0x87, 0x87, 0x83, 0x86, 0x84, 0x86, 0x84], 9)
    #
    # CSI sel and CSI enable
    board.WriteReg(0x32, 0x01) # CSI0 sel and CSI0 enable
    time.sleep(0.5)
    board.WriteReg(0x33, 0x01) # CSI_LANE_COUNT: 4
    time.sleep(0.5)

    # enable pat gen
    board.WriteReg(0xB0, 0x00) # Indirect Pattern Gen Registers
    board.WriteReg(0xB1, 0x01) # PGEN_CTL
    board.WriteReg(0xB2, 0x01)

    board.WriteReg(0xB1, 0x02) # PGEN_CFG
    board.WriteReg(0xB2, 0x35) # NUM_CBARS, Block_size

    board.WriteReg(0xB1, 0x03) # PGEN_CSI_DI
    board.WriteReg(0xB2, 0x1F) # YUV422_10 Data Type

    board.WriteReg(0xB1, 0x04) # PGEN_LINE_SIZE1: 1920*20/8=4800
    board.WriteReg(0xB2, 0x12)

    board.WriteReg(0xB1, 0x05) # PGEN_LINE_SIZE0: 1920*20/8=4800
    board.WriteReg(0xB2, 0xC0)

    board.WriteReg(0xB1, 0x06) # PGEN_BAR_SIZE1: 1920*20/8/8)=600
    board.WriteReg(0xB2, 0x02)

    board.WriteReg(0xB1, 0x07) # PGEN_BAR_SIZE0: 1920*20/8/8)=600
    board.WriteReg(0xB2, 0x58)

    board.WriteReg(0xB1, 0x08) # PGEN_ACT_LPF1: 1080
    board.WriteReg(0xB2, 0x04)

    board.WriteReg(0xB1, 0x09) # PGEN_ACT_LPF0: 1080
    board.WriteReg(0xB2, 0x38)

    board.WriteReg(0xB1, 0x0a) # PGEN_TOT_LPF1: 1125
    board.WriteReg(0xB2, 0x04)

    board.WriteReg(0xB1, 0x0b) # PGEN_TOT_LPF0: 1125
    board.WriteReg(0xB2, 0x65)

    board.WriteReg(0xB1, 0x0c) # PGEN_LINE_PD1:1s/(30*1125*20ns)=1481
    board.WriteReg(0xB2, 0x05)

    board.WriteReg(0xB1, 0x0d) # PGEN_LINE_PD0:1s/(30*1125*20ns)=1481
    board.WriteReg(0xB2, 0xc9)

    board.WriteReg(0xB1, 0x0E) # PGEN_VBP: 33
    board.WriteReg(0xB2, 0x21)

    board.WriteReg(0xB1, 0x0F) # PGEN_VFP: 10
    board.WriteReg(0xB2, 0x0A)

    Best Regards,
    Amy Luo

  • 0 in reply to Amy Luo
    TI__Prodigy 620 points

    Hi Amy,

    Sorry seems I missed the link above... please refer to it here.

    http://www.ti.com/lit/an/snla267a/snla267a.pdf

    And for the pattern generation, we have some script files of ALP, typically you can find it at folder below after install the ALP tools.  

    C:\Program Files (x86)\Texas Instruments\Analog LaunchPAD v1.57.0010\PreDefScripts

    BTW, currently you can find a similar script of 954 here for reference, just don't have the 960 version this moment.

    Thanks & BRs,

    Cheney

  • 0 in reply to Cheney Hu
    TI__Expert 6895 points

    Hi Cheney,

    Thank you for your reply.

    At present, after modifying DS90UB960-Q1, reg 0x58 and 0x5C (original 0x5e), it is found that images can be obtained continuously (24.7fps), but still for a period of time (3-5 sec), the signal will be cut off and the signal transmission will be stopped!

    Will this part be a problem in the hardware circuit, or should the settings be adjusted?? Could you provide debugging suggestions?

    Best Regards,
    Amy Luo

  • 0 in reply to Amy Luo
    TI__Expert 3390 points

    Hi Amy,

    So, the stream start but after 2-3 seconds it stops? I would expect the stream to continue unless the SoC is intentionally set-up to only take in frames for 2-3 seconds and then stop.

    You seem to be capturing data from an imager, did you try running patgen? If so, what were the results, is the stream stopping after 2-3 seconds?

    Also, refer to section 7.4.25.8 in the DS90IB960-Q1 datasheet for the correct procedure on how to enable/disable CSI transmitter.

    0x58 = 0x5E is the correct value if you are using 953/960. This sets the BC frequency to 50Mbps, all you did by changing it to 0x5d is change the Back channel frequency, which you should not do. What is the document that you are referring to here? It may be outdated.

    Regards,
    Mandeep Singh

  • 0 in reply to Mandeep S
    TI__Expert 3390 points

    Hi Amy,

    Do you still need support for this topic? or have any further questions for us? Please know that responses my delayed due to holidays.

    Regards,
    Mandeep Singh

  • 0 in reply to Mandeep S
    Intellectual 475 points

    Hi Mandeep,

    Setting 0x58@960 = 0x5D is the recommendation of TI's Design Guide: TIDA-020002.

    In section 3.1.2 there can be found:

    – Register 0x58 with 0x5D: I2C passthrough enabled and backchannel frequency select.

    At 960 data sheet 0x58[2:0] = 101 is reserved and it seems that this value leads to a 953-960 BC rate of 25Mbps.

    But I suppose 0x5D should not be used, correct is 0x5E for 50Mbps?

    Regards

    Torsten

  • 0 in reply to Torsten Dr. Kilias
    Intellectual 475 points

    Hi Mandeep,

    additional to last comment:

    In updated Analog Launch PAD:

    At "Registers" drop down menue of DS90UB960 value 0x5D is no longer reserved!

    Regards

    Torsten

  • 0 in reply to Torsten Dr. Kilias
    TI__Expert 3390 points

    Hi Torsten,

    Yes, that is correct, you should have the BC speed as 50Mbps for 4G operation. In terms of ALP, the datasheet should be followed, we'll have to update that to match the datasheet.

    Regards,
    Mandeep Singh

  • 0 in reply to Mandeep S
    TI__Expert 3390 points

    Hi Torsten,

    Do you have any further questions regarding this post?

    Regards,

    Mandeep Singh

  • 0 in reply to Mandeep S
    Intellectual 475 points

    Hi Mandeep,

    BC frequency cannot be set to 50Mbps, only 25Mbps works.

    May be there is a dependancy between Clock and BC frequency?

    Regards

    Torsten 

  • 0 in reply to Torsten Dr. Kilias
    TI__Expert 3390 points

    Hi Torsten,

    Can you expand on what you mean by why you are unable to set 50Mbps? You mean your system does not work if you have it at 50Mbps? or your unable to change the register?

    In sync mode, if you want a forward channel of 4G, then you have to use 50Mbps. Using 25Mbps will result in a 2G forward channel.

    Regards,

    Mandeep Singh

  • 0 in reply to Mandeep S
    Intellectual 475 points

    Hi Mandeep,

    we are surely able to change the register, but it does not work then.

    We used the configuration of TI for :

    960: [IMX390_D3_DES_CFG_SIZE] 

    {0x58, 0x5D, 0x10}, /*Enable Back channel, set to 50Mbs*/ - with incorrect comment!

    953:[IMX390_D3_SER_CFG_SIZE] 

    {0x06, 0x21, 0x1F},
    {0x07, 0x28, 0x1F},

    This leads to CLK_OUT =24MHz and FC = 1,92GHz, hence BC should be correct with 25Mbps and 50Mbps should not work?

    Regards

    Torsten

  • 0 in reply to Torsten Dr. Kilias
    TI__Expert 3390 points

    Hi Torsten,

    I want to align, what rate do you want the Forward channel? If you want 2G, then the 25Mbps is okay to use. In sync mode, the back channel will speed of either 25Mbps or 50Mbps will set the forward channel rate. Therefore, a 25Mbps BC will give you a 2G Forward Channel.

    Regards,
    Mandeep Singh