DS90UB926Q-Q1: STS register

Hi,

We are using ds90ub926-q1 deserializer with ds90ub929-q1 serializer.

In the documentation of the ds90ub926, we can read that the bit 7 of register 0x23 is "RX RGB Checksum Enable Setting this bit enables the Receiver to validate a one-byte checksum following each video line. Checksum failures are reported in the STS register".

Could you indicate the address of the STS register where we can read the RGB checksum failures?

Thanks,

Julie