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Hi team,
My customer use DP83822I phy in their system. Why DP83822I recieve wrong package when DP83822I worikng on communication. Most time it recieve wrong package but some time recieve right package.
We read all DP83822I register by MDIO. like below pic. Do you have any suggestions?
We also check the hardware, and we also let INT/PWDN_N pull up. But it stlll not be dealt with. Do you have any suggestions?
Thanks!
Below is register and SCH.
SCH:
Hello,
Do you have the full schematic and pinout for the DP83822? I can only see the pinouts for MII in this portion.
Thanks,
Cecilia
Hi Cecilia,
MII is connect to FPGA directly and there are not Series resistance in MII line.
The MII signal traces long is 8 inches between FPGA and PHY.Is this information enough?
Thanks!