SN65DPHY440SS: Interface forum

Antoine Grodent

Part Number: SN65DPHY440SS

Hello,

As introduced in the title, I wish to use the SN65DPHY440SS retimer at its max data rate (1.5 Gbps/lane) for the transmission of a MIPI CSI-2 signal over two lanes (+clock).We want to use a camera as a MIPI emitter and a Jetson Xavier dev board as a MIPI receiver.

For our design, the retimer will be located approx 20 cm away from the emitter but really close to the receiver (5 cm max).

For these requirements, I wonder after having read the datasheet what would be the advised settings to use in the retimer, especially concerning the ERC, PRE_CFG1 and VSADJ_CFG0 pins?

Thank you for your answer,

over 5 years ago

0 David (ASIC) Liu over 5 years ago

TI__Guru**** 178126 points

I would have pullup and pulldown resistors on EQ, ERC, PRE_CFG1 and VSADJ_CFG0 pins.

EQ compensates for the insertion loss of the 20cm trace.

For PRE_CFG1 and VSADJ_CFG0, please refer to Table 3 for the different configurations. Since DPHY440 is closer to the receiver, you can set the TX pre-emphasis to 0dB as the default value.

ERC can be set to VIM and tweak later if needed.

Thanks

David