HD3SS3411: Clock Terminatio Scheme for LVDS, HCSL Input and Output - Reg.

Hi.

I am using this IC for clock distribution (100MHz) of PCIe Gen 2 section of my design. In that, I have four cases which this IC need to support.

1. LVDS Input with HCSL Output (In any one of the output)

2. LVDS Input with LVDS Output (In any one of the output)

3. HCSL Input with LVDS Output (In any one of the output)

4. HCSL Input with HCSL Output (In any one of the output)

I want to know the termination scheme of each cases on both input and output side.

Kindly help in this regard.

Thanks in advance for your valuable reply.

Regards,

Santhana Krishnan