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DS160PR410: DS160PR410 EQ setting with PCIe Gen 4 compliance test Fail

Edward Kuo1
Prodigy 130 points
Part Number: DS160PR410

We design use 2 IC, one for TX signal (DS160PR410 IC 01), other for RX (DS160PR410 IC 02).

We test PCIe Gen 4 was fail with below Items

Tx preset9 

PLL_BW

L0_EqRx_16GTps_Comp_2.11.2

L0_EqTx_16GTps_Comp_2.4.2

Based on TI FAE reply

1. VOD set to L3 with TX(IC 01) and RX(IC 02) both, this is for EqRx fail item improve.

2. EqTx fail item improve, suggestion our change TX(IC 01) EQ from Index 2 to Index 10.

3. PLL fail item improve, suggestion our change EQ to index 0 or 1

We have problem for the PLL and Tx preset9

1. About the PLL : If we need pass EqTx so setting the TX(IC 01) change to index 10. How to set to index 0or 1.

2. Your mean the PLL and EqTx fail issues, it need with the difference solutions.

3. Could we only change the RX(IC 02) change to index 0 or 1, and

3. How about the Tx preset9 fail item improve.

 

  • 0
    TI__Expert 7975 points

    Hello-

    1. Tx preset9 issue:   In this test, your device PCIe TX sends a signal with a preset 9.  This signal passes through a DS160PR410.  Is this IC 01 or IC 02?  The DS160PR410 receiving preset 9 should set VOD = 3.

    2.  PLL_BW  issue:  In this test, your device PCIe TX frequency response is tested as a function of (sinusoidal) jitter added to the reference clock feeding into your device.  The PCIe TX sends a signal with the added jitter to the instrument that can measure the frequency response.  The signal also passes through a DS160PR410.  Is this IC 01 or IC 02?   What is the channel loss between the PCIe TX and the DS160PR410 RX in test?  Normally, there is not much loss, thus recommendation to set it to Index 0 or 1.  If there is significant channel loss, then the EQ gain on the DS160PR410 RX may be increased.

    3. L0_EqRx_16GTps_Comp_2.11.2:  In this test, a BERT generator sends a P6 signal and your device RX receives it and loops it back to its TX and then forwards it to the BERT checker .  The signal also passes through two  DS160PR410 devices.   What is the channel loss between the generator (P6 source) and the first DS160PR410 RX in the  test?  What is the channel loss between your device TX and the second DS160PR410 RX in the  test?

    Regads,

    Davor

  • 0 in reply to Davor Glisic
    Prodigy 130 points

    Hello Davor

    Our Product is AIC device

    1. About the TX preset 9 We retry adjust VOD = L3, IC 01 and IC 02, still fail this item, but very close the min require. I have try to set L0 and L1 on IC 02(Device RX) is Passed.

    2. PLL_BW issue we try adjust EQ to  Index 0 and  index 1 on IC 02(Device RX), Index 0 is Passed, Index 1 fail

    3. About the L0_EqRx_16GTps_Comp_2.11.2, we try EQ adjust to Index 10 on IC 01(Device TX),

    We want to know the PLL_BW

    Due to the test we can Passed the is with Pattern P7, but general test use the P4

    Did you can provide the P0~P10 SPEC, and difference point for us.

    Can you provide the official documentation of the PCIe SIG test the PLL BW, test P0-P10 pattern as long as pass one of them.

    Thank a lot.